MSM514262 datasheet(42/45 Pages) OKI

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Pseudo Write Transfer Operation

Pseudo write transfer cycle must be performed before loading data into the serial register after

a read transfer operation has been excuted. The only purpose of a pseudo write transfer is to

change the SAM port mode from output mode to input mode (A data transfer from SAM to

RAM does not occur). After the serial register is loaded with new data, a write transfer cycle

must be performed to transfer the data from SAM to RAM. A pseudo write transfer is invoked

by holding CAS “high”, DT/OE “low”, WB/WE “low”, SE “high” and DSF “low” at the falling

edge of RAS. The timing conditions are the same as the one for the write transfer cycle except

for the state of SE at the falling edge of RAS.

Split Data Transfer and QSF

The MSM514262 features a bidirectional split data transfer capability between the RAM and

SAM. During split data transfer operation, the serial register is split into two halves which can

be controlled independently. Split read or write transfer operation can be performed to or from

one half of the serial register while serial data can be shifted into or out of the other half of the

determine which half of the serial register will be reloaded from the RAM. QSF is an output in

which indicates which half of the serial resister is in an active state. QSF changes state when the

last SC clock is applied to active split SAM.

Split Read Transfer Operation

Split read transfer consists of loading 256 words by 4 bits of data from a selected row of the split

RAM into the corresponding non-active split SAM register. Serial data can be shifted out from

of the other half of the split SAM register simultaneously. During split read transfer operation,

the RAM port input clocks do not have to be synchronized with the serial clock SC, thus

eliminating timing restrictions as in the case of real time read transfers. A split read transfer can

be performed after a delay of tSTS, from the change of state of the QSF output, is satisfied.

Conventional (non-split) read transfer operation must precede split read transfer cycles.

Split Write Transfer Operation

Split write transfer consists of loading 256 words by 4 bits of data from the non-active split SAM

other half of the split SAM register simultaneously. During split write transfer operation, the

RAM port input clocks do not have to be synchronized with the serial clock SC, thus allowing

for real time transfer. A split write transfer can be performed after a delay of tSTS, from the

change of state of the QSF output, is satisfied.

A pseudo write transfer operation must precede split write transfer. The purpose of the pseudo

write transfer operation is to switch the SAM port from output mode to input mode and to set

the initial TAP location prior to split write transfer operations.

Transfer Operation Without CAS

During all transfer cycles, the CAS clock must be cycled, so that the column addresses are

latched at the falling edge of CAS, to set the SAM TAP location.

MSM514262 Datasheet(PDF) 42 Page - OKI electronic componets