DAC

+

±

+

±

ADC

+

±

Force

Amplifier

TMUX6136

DUT

B

B

A

A

Current

Sense

Amplifier

Voltage

Sense

Amplifier

Av

DAC

+

±

+

±

ADC

+

±

Force

Amplifier

TMUX6136

DUT

B

B

A

A

Current

Sense

Amplifier

Voltage

Sense

Amplifier

Av

21

TMUX6136

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Typical Application (continued)

8.2.1 Design Requirements

The goal of this design example is to simplify the FVMC and FCMV functions of a PMU design using a SPDT

switch. The FVMC configuration is useful to test a device being used as a power supply, or in continuity or

leakage testing. In this configuration, the input voltage is directly applied to the DUT pin, and the current into/ out

of the DUT pin is converted to a voltage by a sense resistor and measured by an analog to digital converter

(ADC). In the FCMV mode, an input current is forced to the DUT and the produced voltage on the DUT pin is

directly measured. In this example, the PMU design is required to meet the following specifications:

•

Force voltage range: –15 volts to +15 volts

•

Force current range: ±5 µA to ±50 mA

•

Measure voltage range: –15 volts to +15 volts

•

Measure current range: ±5 µA to ±50 mA

In additional to the voltage and current requirements, fast throughput is also a key requirements in ATE because

it relates directly to the cost of manufacturing the DUT.

8.2.2 Detailed Design Procedure

Figure 34. FVMC Implementation in PMU Using the

TMUX6136

Figure 35. FCMV Implementation in PMU Using the

TMUX6136

The FVMC and FCMV modes implementations can be combined with the use of a dual SPDT switch such as the

TMUX6136. Figure 34 and Figure 35 shows simplified diagrams of such implementations. In the FVMC mode,

the switch is toggled to position A and this allows the voltage sense amplifier to become part of the feedback

loop and the voltage output of the current sense amplifier to be sampled by the ADC. In the FCMV mode, the

switch is toggled to position B, and this allows the current sense amplifier to become part of the feedback loop

and the voltage output of the voltage sense amplifier to be sampled by the ADC.