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UP1817PDDA Datasheet(PDF) 4 Page - uPI Group Inc.

Part # UP1817PDDA
Description  2-Channel SVID-Controlled Reference Generator in
PDF  21 Pages
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Manufacturer  UPI [uPI Group Inc.]
Direct Link  http://www.ubiq-semi.com/
Logo UPI - uPI Group Inc.

UP1817PDDA Datasheet(HTML) 4 Page - uPI Group Inc.

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uP1817
4
uP1817-DS-F0000, Mar. 2017
www.upi-semi.com
Functional Description
Supply Input
The uP1817 operates with a well regulated supply input at
VCC pin. A minimum 0.1uF ceramic capacitor physically
placed near the VCC pin is required for locally by-passing
the supply input. The VCC voltage is continuously monitored
for power on reset function (POR). The typical POR level
is 4.2V at VCC rising. After VCC POR, the uP1817 initiates
the boot up sequence. When the VCC pin voltage is lower
than the POR threshold, the uP1817 is disabled.
Operation Mode and SVID VR Address
The uP1817 supports two operation modes (IMVP8 mode
and VR12.1 mode). Connect a resistor divider from VCC
pin to MODE pin to select the operation mode as shown in
Figure 1. The controller detects the MODE pin voltage at
VCC POR to determine the operation mode and latch at
the selected mode. Table 1 shows the operation mode,
SVID VR address, and the content in SVID register 0x21h
(Iccmax) in each mode. The spec required minimum voltage
rising slew rate (fast) for VR12.1 is 10mV/us, and it is 30mV/
us for IMVP8. For uP1817, the actual reference output
voltage rising/falling slew rate (fast and slow) is determined
by the internal circuit. Use a 0.1uF MLCC as the timing
capacitor connected from VREF to GND to meet the spec.
The output voltage fast slew rate for ALERT# assertion is
30mV/us for VR12.1 and IMVP8. The ALERT# assertion
timing is determined internally. The slew rate of reference
voltage change is faster than that for alert assertion to
ensure reference voltage is settled before alert assertion.
Table 1 . Operation Mode Selection
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Enable and Initial Start Up Voltage Vboot
The EN/VBOOT pin is a multi-functional pin. This pin
provides enable/disable control for power sequence design
flexibility, and it is also used to determine the initial start
up output voltage Vboot. Logic high input to the EN/VBOOT
pin enables the controller, and logic low to this pin disables
the controller.
The uP1817 supports hardware selectable initial start up
output voltage Vboot, which is determined by the resistor
voltage divider connected from VCC to EN/VBOOT pin as
shown in Figure 1. There are four Vboot levels to choose
from. Table 2 shows the recommended resistor voltage
divider resistance value and the corresponding Vboot
voltage.
MODE
A/D
Converter
EN/VBOOT
R3
R4
VCC
Enable/Disable
Control
R1
R2
VCC
Figure 1. Operation Mode and Vboot Voltage Selection
Table 2. Vboot Voltage Selection
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Power On Sequence
The uP1817 supports zero Vboot and non-zero Vboot
setting. In each case both VR12.1 mode and IMVP8 mode
share the similar power on sequence.
Figure 2 shows the power on sequence of zero Vboot case
in VR12.1/IMVP8 mode. Once VCC is ready, the controller
waits for logic input high to EN/VBOOT. After EN/VBOOT
goes high, the controller initializes start up sequence. There
is a waiting time Ta from EN/VBOOT goes high to the
controller is ready to accept SVID command. At the end of
Ta, the reference voltage outputs (VREF0 and VREF1) ramp
up to 0.32V and wait for 1st SetVID command. ALERT#
remains high at this phase. Then a SetVID command is
sent to address 00h, making VREF0 ramps up to target
VID voltage with slewing time Tb (Tb is determined by the
sourcing current and timing capacitor). ALERT# is asserted
after internally calculated time duration Tc. To ensure
Tb<Tc, it is recommended to use 0.1uF as timing capacitor.
Then the processor sends a GetReg(10h) command to clear
the ALERT#.



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