MSM5299 datasheet(8/11 Pages) OKI

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MSM5299C

¡ Semiconductor

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•D0, D1, D2, D3

Display data input pins for 4¥20-bit shift register. The display data is clocked into these pins.

The combinations of D0 to D3, DF signal level, display data output level and the display on

the LCD panel are described in the table below.

D0 - D3

Liquid crystal drive output

Non-select level (V3)

Select level (V1)

Non-select level (V4)

Select level (VEE)

Liquid crystal dispaly

OFF

• LOAD

The signal for latching the shift register contents is input to this pin. The display data stored

in the shift register is latched at the falling edge of the LOAD pulse.

•DF

Alternate signal input pin for LCD driving. Frame inversion signal is input to this pin.

•VDD, VSS

Supply voltage pins. VDD should be 4.5 to 5.5V. VSS is a ground pin (VSS = 0V).

•V1, V3, V4, VEE

Bias supply voltage pin to drive the LCD. Bias voltage to drive the LCD is supplied from an

external source.

MSM5299 Datasheet(PDF) 8 Page - OKI electronic componets