MP5403B

– DUAL BUCK AND ONE LOAD SWITCH PMIC

MP5403B Rev. 1.0

www.MonolithicPower.com

18

12/5/2017

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© 2017 MPS. All Rights Reserved.

Table 1: Output Discharge Conditions

Output Discharge

VIN

EN

No

>UVLO

High

Yes

>UVLO

Low

Yes

<UVLO

High

Yes

<UVLO

Low

Power Good (PG) Indicators

The MP5403B has three separate power good

(PG), open-drain, output indicators for the

regulators and load switch. For the two step-

down regulators, when FB is in the regulation

window (between 90% to 130% of the reference

voltage, 0.6V), PG1 and PG2 pins are pulled up

to the external bus voltage through certain

external resistors. The pull-up resistors are

recommend not to be too low to ensure that the

leakage current is small when the PG pins are

low and not too high if they are used to drive

downstream signals. Normally, pull-up resistors

between

10kΩ to 400kΩ are sufficient. The PG

rising delay is around 20µs. If the FB voltage

drops below 90% or rises above 130% of the

reference voltage, the PG pins are pulled down

to ground by an internal MOSFET. The MOSFET

is also a 60µs delay for the PG falling threshold

trigger.

The power good pin for the load switch (PG3) is

pulled high when the input voltage of the load

switch (VIN3) is higher than its UVLO threshold,

the output voltage (VOUT3) is less than 200mV

compared with the input voltage of the load

switch, and there is around 40µs of rising delay

for the PG3 indicator. If any of these three

conditions are not met, PG3 is pulled low.

The PG indicators are pulled low when VIN1 is

below UVLO. In this condition, the PG pins are

self-driven low (around 0.6V).

Power Failure Indicator (PFL)

The power failure indicator (PFL) senses the

external voltage rails. When the input voltage is

below the programmed threshold, the PFL open-

drain output is pulled low immediately to indicate

the monitored power failure. PFL_ADJ is used to

adjust the power failure threshold voltage. A

resistor divider is used to monitor the voltage rail.

When the PFL_ADJ voltage is lower than 0.6V,

PFL is pulled down to indicate the sense power

failure. When the PFL_ADJ voltage is higher

than the 0.6V reference voltage, PFL is pulled

s

μ

5

.

3

+

)

A

μ

(

I

62

.

0

×

)

pF

(

C

=

)

s

μ

(

T

DELAY

DELAY

DELAY

(1)

3.1µA).

Current Limit

The MP5403B has a high-side 6.2A current limit

for the first regulator and a 5A current limit for the

second regulator. When the high-side switch

reaches

the

current-limit

threshold,

the

regulators shut down the high-side switch and

force the low-side switch on until the low-side

current drops to the low-side valley current

threshold (peak 5A and peak 4A for the two

regulators). After the low-side current reaches

the valley current threshold, the high-side switch

can turn on again. If the high load current

persists, the high-side turns on again, and the

current-limit mechanism repeats until the output

voltage drops to the short-circuit threshold. If the

high-load current does not persist, then the

regulator resumes normal conditions.

For the load switch, the current limit begins

working when the load switch current reaches

the current-limit threshold. The gate is pulled low

to regulate the load switch current to the current

limit. The output voltage drops until thermal

shutdown occurs.

Short Circuit and Recovery

When CH1 or CH2 is in buck mode, the

MP5403B enters short-circuit protection (SCP)

mode when the inductor current reaches the

current limit for 300µs continuously or the output

voltage drops below 50% of the regulation

voltage. In SCP mode, the MP5403B disables

the output power stage, discharges the soft-start

capacitor, and enters latch-off protection mode.

The MP5403B restarts by recycling the power.