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MPM3530 Datasheet(PDF) 16 Page - Monolithic Power Systems

Part # MPM3530
Description  55V, 3A, Step-Down Power Module
PDF  20 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MPM3530 Datasheet(HTML) 16 Page - Monolithic Power Systems

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MPM3530
– 55V, 3A, STEP-DOWN POWER MODULE
MPM3530 Rev. 1.0
www.MonolithicPower.com
16
9/21/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
3. C3 can be calculated with Equation (19):
C
f
R3
2
π
4
C3
(19)
Determine if C4 is required. C4 is required if
the ESR zero of the output capacitor is
located at <0.5xfSW, or Equation (20) is
valid:
2
f
R
C2
2
π
1
SW
ESR
(20)
If this is the case, use C4 to set the pole
(fP3) at the location of the ESR zero.
Determine C4 with Equation (21):
R3
R
C2
C4
ESR
(21)
External Bootstrap Diode
For high duty-cycle operations where VOUT/VIN >
65%, there is less time available for the
bootstrap charging, so the bootstrap capacitor
may not be charged sufficiently. This affects
efficiency and normal operation. An external
bootstrap diode from the 3 - 5V rail to BST can
help
charge
the
bootstrap
capacitor
and
enhance efficiency (see Figure 2). The output
voltage is a good choice for this power supply if
it is in the above range. The bootstrap diode
can be a low-cost one, such as IN4148 or
BAT54.
CBST
COUT
L
BST
SW
3V-5V Rail
1N4148
VOUT
Figure 2: External Bootstrap Diode
At no load or light load, the converter may
operate in pulse-skip mode to maintain the
output-voltage regulation. Under this condition,
VSW = VOUT for most of the time, so the diode
from VOUT to BST cannot charge the bootstrap
capacitor. For a sufficient gate voltage during
pulse-skip mode, VIN - VOUT should be no less
than 3V. For example, if VOUT = 3.3V, then VIN
must exceed 3.3V + 3V = 6.3V to maintain a
sufficient bootstrap voltage at no load or light
load. To meet this requirement,
EN can
program the input UVLO voltage to VOUT + 3V.
PCB Layout Guidelines (10)
Efficient
PCB
layout
is
critical for
stable
operation. For best results, refer to Figure 3 and
follow the guidelines below.
1. Keep the connection of the input ground
and GND as short and wide as possible.
2. Ensure that all feedback connections are
short and direct.
3. Place the feedback resistors as close as to
the chip as possible.
4. Route sensitive analog areas such as FB
away from SW.
5. Place enough vias around the chip for better
thermal performances.



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