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MPM3530 Datasheet(PDF) 3 Page - Monolithic Power Systems

Part # MPM3530
Description  55V, 3A, Step-Down Power Module
PDF  20 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MPM3530 Datasheet(HTML) 3 Page - Monolithic Power Systems

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MPM3530
– 55V, 3A, STEP-DOWN POWER MODULE
MPM3530 Rev. 1.0
www.MonolithicPower.com
3
9/21/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
PIN FUNCTIONS
Pin #
Name
Description
1, 42 - 44
VIN
Input supply. VIN supplies power to all of the internal control circuitries and the VDD
regulator. Place a decoupling capacitor to ground close to VIN to minimize switching
spikes. Use wide traces to connect VIN.
2, 12 - 16,
30, 38, 41,
45, 46
PGND
Module power ground pin.
3
BST
Bootstrap. BST is the positive power supply for the internal floating high-side
MOSFET driver. Keep BST floating.
4 - 11
SW
Switch output. Keep SW floating.
17 - 28, 47
OUT
Module voltage output node. Use wide traces to connect OUT.
29
VDD
Power for internal MOSFET driver and BST charging circuit.
31
PG
Power good indication. Connect a resistor from PG to a pull-up power source if it is
being used.
32
SS
Soft start. Float SS for a default 1.2ms SS time. The SS time can be extended by
connecting an external capacitor between SS and AGND.
33 - 35
AGND
Ground for internal logic and signal circuit.
36
COMP
Compensation networks setting. Connect an external resistor series with a capacitor
between COMP and AGND. See the Application Information section on page 15 for
compensation network configuration details.
37
FB
Feedback. FB is the input to the PWM comparator. Connect an external resistor
divider between the output and AGND.
39
FREQ
Frequency set pin. Connect a resistor from FREQ to ground to set the switching
frequency. If an external SYNC clock is applied to FREQ, the converter follows this
SYNC clock frequency.
40
EN
Enable input. Pull EN below the specified threshold to shut down the chip. There is no
internal pull-up or pull-down circuit, so EN cannot be floated.
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) .....................................60V
VSW .......................................-0.5 to (VIN + 0.5V)
VBST .....................................................VSW + 6V
VOUT ..........................................................16.5V
All other pins.................................... -0.3V to 6V
EN sink current ........................................150
μA
All other pins.................................... -0.3V to 4V
Continuous power dissipation (TA = +25°C)
(2)
.....................................................................5W
Junction temperature ............................... 150°C
Lead temperature .................................... 260°C
Storage temperature.................. -65°C to 150°C
Recommended Operating Conditions
(3)
Supply voltage (VIN) ........................ 4.5V to 55V
Output voltage (VOUT)......................... 1V to 15V
Operating junction temp. (TJ) ... -40°C to +125°C
Thermal Resistance
θJA
θJC
QFN-47 (10mmx12mmx4mm)
EVM3530-RF-01A
(4)............. 17..... 3.4 .... °C/W
JESD51-7
(5) ......................... 17..... 7.4 .... °C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θ
JA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on EVM3530-RF-01A,4-layer PCB, 76mmx76mm.
5)
The value of θ
JA given in this table is only valid for comparison
with other packages and cannot be used for design purposes.
These values were calculated in accordance with JESD51-7
and simulated on a specified JEDEC board. They do not
represent the performance obtained in an actual application.



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