MSM548333 datasheet(13/42 Pages) OKI

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MSM548333

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MSM548333's read operation is achieved in "line by line" manner.

Any read operations are prohibited in the initial read address set periods. Serial read

operations for Y1 and C1, and also Y2 and C2, are prohibited while RADE1/RX is high.

Similarly, serial read operations for Y1 and C1, and also Y2 and C2, are prohibited while

RADE2/RX level is high. Y1 and C1 Serial read port enable time tSRE1, Y2 serial read port

enable time tSREY2 and C2 serial read port enable time tSREC2 must be kept for starting a serial

read just after the initial read address set period.

Initial Address Reset Modes (Write/Read Independent)

The initial address reset modes replace complicated read or write initial address settings with simple

reset cycles. Initial address reset modes are selected by RR/TR high during read and WR/TR high

during write. As in normal read or write address settings, any read operations are prohibited in the

read address reset cycles. Similarly, any write operations are prohibited in the initial write address

resetcycles.Notethatreadinitialaddressresetandwriteinitialaddressresetcanoccurindependently.

Similarly, read access can be achieved independently from write initial address reset cycles and write

access can be achieved independently from read initial address reset cycles.

Input addresses are stored into address registers which are connected with address counter which

controls address pointer operation. In the serial access operation, the input address into the address

registers are kept.

Serial write data input enable time tSWE, Y1 and C1 read port read enable time tSRE1, Y2 serial read

port read enable time tSREY2, C2 serial read port read enable time tSREC2 must be kept for starting

serial read or write just after the initial read or write address reset cycles. Note that all the read ports'

initial address reset must occur with the same timing.

1. Original address reset No.1 - "X, Y address counter reset" -

By the "Original address reset No.1" logic which is composed by a combination of control

input' levels, the address counter is reset to (0,0), and then, the address pointer is initialized

to (0,0). Reference the "FUNCTION TABLE" for read and write shown later. After the reset

mode, serial access starts from the address (0,0) : the line address is "0" and the initial bit

address on the line is (0,0).

The address counter is reset by this reset mode but the address register, which stored input

addressinthepreviousaddressresetcycleoraddresssetcycle,isnotreset.Thenon-initialized

address can be used as a preset address in "address jump reset" mode. When the address

2. Original address reset No.2 - "X,Y address register reset" -

By the "Original address reset No.2" logic, the address register is reset, and then, the address

counter and address pointer are initialized to address (0,0) automatically. After the reset

mode, serial access starts from the address (0,0) : the line address is "0" and the initial bit

address on the line is (0,0)

Both address register and address counter are reset to (0,0) and the stored initial address in the

previous address reset cycle or address set cycle is cleared by this "address register reset". Once

the reset mode is selected, the reset address (0,0) is stored in the address register as a preset

address until next initial address set or reset operation. The address can be used as a preset

address in the "address jump reset" mode.

Note that REY2/RY and REC2/C2 must be both "L" at the same time when the "address

RY = "L" are prohibited.

3. Original address reset No.3 - Y address counter reset" -

By the "Original address reset No.3" logic, the Y address register is reset, and then, address

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