STC15F103 datasheet(21/252 Pages) ETC2

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Chapter 2 Clock, Power Management, Reset

2.1 Clock

There is only one clock source—Internal RC oscillator available for STC15F204EA series.

After picking out clocking source, there is another slow-down mechanism available for power-saving purpose.

User can slow down the MCU by means of writing a non-zero value to the CLKS[2:0] bits in the CLK_DIV

CLKS[2:0] to a non-zero value before entering the idle mode.

CLK_DIV register (Clock Divider)

LSB

SFR Name SFR Address

bit

CLK_DIV

97H

name

CLKS2 CLKS1 CLKS0

{CLKS2,CLKS1,CLKS0}

000 := The internal RC oscillator is set as the clock-in not divided (default state)

001 := The internal RC oscillator is set as the clock-in divided by 2

010 := The internal RC oscillator is set as the clock-in divided by 4

011 := The internal RC oscillator is set as the clock-in divided by 8

100 := The internal RC oscillator is set as the clock-in divided by16

101 := The internal RC oscillator is set as the clock-in divided by 32

110 := The internal RC oscillator is set as the clock-in divided by 64

111 := The internal RC oscillator is set as the clock-in divided by 128

Not-divided

÷2

÷4

÷8

÷16

÷32

÷64

÷128

CLKS2,CLKS1,CLKS0

000

001

010

011

100

101

110

111

System clock (SYSclk)

(To CPU and peripherals)

Clock Structure

Internal RC oscillator

(5 MHz — 35 MHz)

(temperature drifting ±1%)

STC15F103 Datasheet(PDF) 21 Page - List of Unclassifed Manufacturers

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