LM5176PWPR datasheet(4/37 Pages) TI1

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LM5176

SNVSAI1A – JUNE 2017 – REVISED MARCH 2019

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Pin Functions

I/O

DESCRIPTION

NAME

HTSSOP

QFN

EN/UVLO

Enable pin. For EN/UVLO < 0.4 V, the LM5176 is in a low current shutdown mode. For

EN/UVLO > 1.22 V, the PWM function is enabled, provided VCC exceeds the VCC UV

threshold.

VIN

I/P

The input supply pin to the IC. Connect VIN to a supply voltage between 4.2 V and 55 V.

VISNS

VIN sense input. Connect to power stage input rail.

MODE

1.38 V < MODE < 2.22 V: CCM, hiccup enabled (set RMODE resistor to AGND = 93.1 kΩ)

2.6 V < MODE < VCC: CCM, hiccup disabled (set RMODE resistor to AGND = 200 kΩ or

connect to VCC)

DITH

A capacitor connected between the DITH pin and AGND is charged and discharged with a

current source. As the voltage on the DITH pin ramps up and down the oscillator frequency

is modulated by 10% of the nominal frequency set by the RT resistor. Grounding the DITH

pin will disable the dithering feature. In the external Sync mode, the DITH pin voltage is

ignored.

RT/SYNC

Switching frequency programming pin. An external resistor is connected to the RT/SYNC

pin and AGND to set the switching frequency. This pin can also be used to synchronize the

PWM controller to an external clock.

SLOPE

A capacitor connected between the SLOPE pin and AGND provides the slope

compensation ramp for stable current mode operation in both buck and boost mode.

Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-

start time.

COMP

Output of the error amplifier. An external RC network connected between COMP and

AGND compensates the regulator feedback loop.

AGND

Analog ground of the IC.

Feedback pin for output voltage regulation. Connect a resistor divider network from the

output of the converter to the FB pin.

VOSNS

VOUT sense input. Connect to the power stage output rail.

ISNS(–)

ISNS(+)

Input or output current sense amplifier inputs. An optional current sense resistor connected

between ISNS(+) and ISNS(–) can be located either on the input side or on the output side

of the converter. If the sensed voltage across the ISNS(+) and ISNS(-) pins reaches 50

mV, a slow constant current (CC) control loop becomes active and starts discharging the

soft-start capacitor to regulate the drop across ISNS(+) and ISNS(–) to 50 mV. Short

ISNS(+) and ISNS(–) together to disable this feature.

CSG

The negative or ground input to the PWM current sense amplifier. Connect directly to the

low-side (ground) of the current sense resistor.

The positive input to the PWM current sense amplifier.

PGOOD

Power-Good open drain output. PGOOD is pulled low when FB is outside a -9%/+10%

regulation window around the 0.8-V VREF.

SW2

SW1

The boost and the buck side switching nodes respectively.

HDRV2

HDRV1

Output of the high-side gate drivers. Connect directly to the gates of the high-side

MOSFETs.

BOOT2

BOOT1

An external capacitor is required between the BOOT1, BOOT2 pins and the SW1, SW2

pins respectively to provide bias to the high-side MOSFET gate drivers.

LDRV2

LDRV1

Output of the low-side gate drivers. Connect directly to the gates of the low-side

MOSFETs.

PGND

Power ground of the IC. The high current ground connection to the low-side gate drivers.

VCC

I/O/P

Output of the VCC bias regulator. Connect capacitor to ground.

BIAS

I/P

Optional input to the VCC bias regulator. Powering VCC from an external supply instead of

VIN can reduce power loss at high VIN. For VBIAS > 8 V, the VCC regulator draws power

from the BIAS pin.

PowerPAD™

—

Solder the PowerPAD to the analog ground. If possible, use thermal vias to connect to a

PCB ground plane for improved power dissipation.

LM5176PWPR Datasheet(PDF) 4 Page - Texas Instruments

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