M0519 datasheet(24/69 Pages) NUVOTON

24 / 69 page

M0519

Nov. 02, 2016

Page 24 of 69

Rev 1.02

FUNCTIONAL DESCRIPTION

ARM

® Cortex® -M0 Core

6.1

The Cortex

® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an

AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug

functionality. The processor can execute Thumb code and is compatible with other Cortex

® -M

profile processor. The profile supports two modes -Thread mode and Handler mode. Handler

mode is entered as a result of an exception. An exception return can only be issued in Handler

mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.

Figure 6-1 shows the functional controller of processor.

CortexTM-M0

Processor

Core

Nested

Vectored

Interrupt

Controller

(NVIC)

Breakpoint

and

Watchpoint

Unit

Debugger

Interface

Bus Matrix

Debug

Access

Port

(DAP)

Debug

CortexTM-M0 processor

CortexTM-M0 Components

Wakeup

Interrupt

Controller

(WIC)

Interrupts

Serial Wire or

JTAG Debug Port

AHB-Lite

Interface

Figure 6-1 Functional Controller Diagram

The implemented device provides the following components and features:



A low gate count processor:

ARMv6-M Thumb

® instruction set

Thumb-2 technology

ARMv6-M compliant 24-bit SysTick timer

A 32-bit hardware multiplier

System interface supported with little-endian data accesses

Ability to have deterministic, fixed-latency, interrupt handling

Load/store-multiples and multicycle-multiplies that can be abandoned and

restarted to facilitate rapid interrupt handling

C Application Binary Interface compliant exception model. This is the ARMv6-M,

C Application Binary Interface (C-ABI) compliant exception model that enables

the use of pure C functions as interrupt handlers

Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event

(WFE) instructions, or the return from interrupt sleep-on-exit feature



NVIC:

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