LD5525 datasheet(10/16 Pages) LEADTREND

10 / 16 page

LD5525

06/30/2015

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD5525-DS-00 June 2015

resonate in discontinuous current mode. The resonance

frequency (FQR) will be obtained as below.

)

(







Inductance of primary winding



Resonance equivalent parasitic capacitance

If VDS voltage falls to resonant valley level from max

plateau value, the QRD comparator will be tripped while

FB pin voltage is close to 100mV.

Voltage Feedback Loop

The voltage feedback signal is provided from the TL431 at

the secondary side through the photo-coupler to the

COMP pin of the LD5525.

Similar to UC3842, the

LD5525 would without voltage offset to feed the voltage

divider at the ratio of RA and RB, that is,

COMP

PWM

COMPARATOR









)

(

A pull-high resistor is embedded internally and therefore

no external one is required.

Current Sensing, Leading Edge Blanking

The typical current mode of PWM controller feedbacks

both current signal and voltage signal to close the control

loop and achieve regulation. The LD5525 detect the

primary MOSFET current from the CS pin, which is not

only for the peak current mode control but also for the

pulse-by-pulse current limit. The

maximum

voltage

threshold of the current sensing pin sets at 0.57V. From

above, the MOSFET peak current can be obtained from

below.

MAX

PEAK

)

(



A 350nS leading-edge blanking (LEB) time is included in

the input of CS pin to prevent the false-trigger from the

current spike. In the low power application, if the total

pulse width of the turn-on spike is less than 350nS and

the negative spike on the CS pin doesn

’t exceed -0.3V, it

could remote the R-C filter (as shown in the figure 9).

However, the total pulse width of the turn-on spike is

decided by the output power, circuit design and PCB

layout.

It is strongly recommended to adopt a smaller

R-C filter (as shown in figure 10) for higher power

application to avoid the CS pin being damaged by the

negative turn-on spike.

Output Stage and Maximum ON Time

An output stage of a CMOS buffer, with typical 250mA

driving capability, is incorporated to drive a power

MOSFET directly.

And the maximum on time of LD5525

is limited to 15us to limit the minimum frequency of the

system.

Maximum Switching Frequency Clamp

According to the QR operation principle, the switching

frequency is inversely proportional to the output power.

Therefore, as the output power decreases, the switching

frequency can become rather high without limiting. The

maximum switching frequency of LD5525 is clamped at

65 kHz internally to provide the optimized operations by

considering the EMI performance, thermal treatment,

component sizes and transformer design.

VCC

GND

LD5525

Can be removed if the negative

spike is not over spec. (-0.3V).

OUT

350ns

blanking

time

Fig. 9

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