¡ Semiconductor

MSM7582/7582B

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PIN AND FUNCTIONAL DESCRIPTIONS

TXD

Transmit data input for 384 kbps.

TXCI

Transmit clock input.

When the control register CR0 – B6 is “0”, a 384 kHz clock pulse synchronous with TXD should

be input to this pin. This clock pulse should be continuous because these devices use APLL to

generate the internal clock pulse.

When CR0 – B6 is “1”, a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz

clock pulse is applied, TXCO outputs a 384 kHz clock pulse, which is generated by dividing the

3.84 MHz to TXCI by 10. The transmit data, synchronous 384 kHz clock pulse, should be input

to the TXD. In this case the devices do not use APLL, and the 3.84 MHz clock pulse need not be

continuous. (Refer to Fig. 1.)

TXCO

Transmit clock output.

When CR0 - B6 is “0”, TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring

purposes. When CR0 – B6 is “1”, this pin outputs a 384 kHz clock pulse generated by dividing

the TXCI input by 10. (Refer to Fig. 1.)

When CR0 – B6 = “0” and CR5 – B7 = “1”, this pin outputs the burst timing position.

TXW

Transmit data window input.

The transmit timing signal for the burst data is input to the device pin. If TXW is “1”, the

modulation data is output. However, the MSM7582 is different from the MSM7582B in the ramp

response time for burst rise-up and burst fall-down of I, Q modulated outputs, as shown in the

table below. (Refer to Fig, 1-1 for the MSM7582 and Fig, 1-2 for the MSM7582B)

MSM7582

MSM7582B

Ramp Rise-up

1.75 symbols

2 symbols

Ramp Fall-down

2.75 symbols

2 symbols

The TXCO burst position output timing discribed before, is different, according to this table.