¡ Semiconductor

MSM7582/7582B

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ENV

Quadrature modulation signal envelope (

: R

≥ 10 kW, C ≤ 20 pF. The gain of this output can be adjusted using the control register CR2 – B7

to B4.

This pin is also used to monitor eye pattern, AFC Compensating signal, and phase defection of

the demodulator block during the test mode. Refer to the description of the control register for

details.

SG

Internal reference voltage output.

The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin and

the AGND pin.

PDN0, PDN1, PDN2

Inputs for power-down control.

PDN0 controls the standby / communication modes, PDN1 controls the modulator, and PDN2

controls the demodulator. Refer to Table 1 for details.

Table-1 Power Down Control

PDN0

Standby

Mode

Communication

Mode

PDN2 PDN1

0

0/1

1

010

100

101

110

111

Function

All power-down. The control register is reset.

Modulator power is off (VREF and PLL power are also off).

Demodulator power is on.

Modulator power is off (VREF and PLL power is on).

I and Q outputs are in a high-impedance state.

Only demodulator clock recovery block power is on.

Modulator power is on

Only demodulator clock recovery block power is on.

Modulator power is off (VREF and PLL power is on).

I and Q outputs are in a high-impedance state.

Demodulator power is on.

Demodulator power is on.

Modulator power is on

Mode

Mode A

Mode C

Mode D

Mode E

Mode F

Mode G

000

All power-down. The control register is not reset.

Mode B

+3 V power supply voltage.

AGND

Analog signal ground.

DGND

Digital signal ground.

AGND and DGND are not connected in the device. This pin should be tied to the AGND pin on

the PCB as close as possible from the device.