CDC913

PC MOTHERBOARD CLOCK GENERATOR

WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS

SCAS502C – APRIL 1995 – REVISED MAY 1996

5

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25°C

MIN

TYP†

MAX

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

TYP†

MAX

UNIT

VIK

VCC = 3.135 V,

II = –18 mA

–1.2

–1.2

V

IOH = –12 mA

REFCLK

2.5

2.4

IOH = – 6 mA

PCICLK

2.5

2.4

VOH

VCC = 3.135 V

IOH = – 6 mA

CPUCLK

2.5

2.4

V

OH

CC

IOH = –12 mA

1Yn

2.5

2.4

IOH =12 mA

2Yn

25

24

IOH = –12 mA

2Yn

2.5

2.4

IOL = 12 mA

REFCLK

0.4

0.5

IOL = 6 mA

PCICLK

0.4

0.5

VOL

VCC = 3.135 V

IOL = 6 mA

CPUCLK

0.4

0.5

V

OL

CC

IOL = 12 mA

1Yn

0.4

0.5

IOL =12mA

2Yn

04

05

IOL = 12 mA

2Yn

0.4

0.5

II

VCC = 3.6 V,

VI = VCC or GND

±1

±1

µA

IOZ

VCC = 3.6 V,

VO = 3 V or 0

±1

±1

µA

V3 6 V

I0

Outputs high

1

ICC

VCC = 3.6 V,

VI =VCC or GND

IO = 0,

Outputs low

1

mA

VI = VCC or GND

Outputs disabled

1

Ci

VI = 3.135 V or 0

6

pF

Co

VI = 3.135 V or 0

6

pF

† All typical values are at VCC = 3.3 V, TA = 25_C.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

UNIT

Stabilization time‡

After SEL1, SEL0

5

ms

Stabilization time‡

After power up

5

ms

‡ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a

fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and

skew parameters given in the switching characteristics table are not applicable.