CDC913

PC MOTHERBOARD CLOCK GENERATOR

WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS

SCAS502C – APRIL 1995 – REVISED MAY 1996

6

POST OFFICE BOX 655303

switching characteristics (see Figures 1 and 2)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V,

TA = 25°C

VCC = 3.135 V to 3.6 V,

TA = 0°C to 70°C

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

tPLH

1A

1Yn

1.5

3.5

1.2

3.8

ns

tPLH

2A

2Yn

1.5

3.5

1.2

3.8

ns

tPHL

1A

1Yn

1.5

3.5

1.2

3.8

ns

tPHL

2A

2Yn

1.5

3.5

1.2

3.8

ns

tPZH

OE

1Yn

2.5

7

2

7.5

ns

tPZH

OE

2Yn

2.5

7

2

7.5

ns

tPZL

OE

1Yn

2.5

7

2

7.5

ns

tPZL

OE

2Yn

2.5

7

2

7.5

ns

tPHZ

OE

1Yn

2.5

7

2

7.5

ns

tPHZ

OE

2Yn

2.5

7

2

7.5

ns

tPLZ

OE

1Yn

2.5

7

2

7.5

ns

tPLZ

OE

2Yn

2.5

7

2

7.5

ns

1Yn

350

350

tsk(o)

2Yn

350

350

ps

()

Any Y

500

500

tsk(p)

1Yn and 2Yn

1

1

ns

†

CPUCLK

±250

Jitter(pk pk)†

CPUCLK

±250

ps

Jitter(pk-pk)†

PCICLK

±350

s

†

PCICLK

30

†

SEL0 = L,

SEL1 = L

20

tc(period)†

CPUCLK

SEL0 = H,

SEL1 = L

16.7

ns

SEL0 = L,

SEL1 = H

15

D t c cle†

CPUCLK

45%

55%

Duty cycle†

PCICLK

45%

55%

tr‡

2

ns

tf‡

2

ns

† Specifications are applicable only after the PLL stabilization time has elapsed.

‡ Rise and fall times are characterized using the load circuits shown in Figure 1.