INA1650 datasheet(11/41 Pages) TI1

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Time (500 ns/div)

C017

Time (500 ns/div)

C017

Time (2.5 µs/div)

C017

Time (2.5 µs/div)

C017

100

1000

Capacitive Load (pF)

Positive Overshoot

Negative Overshoot

C004

-180

-160

-140

-120

-100

-80

-60

-40

10k

100k

10M

Frequency (Hz)

REF / COM Pins Grounded

REF / COM Pins Connected to VMID(OUT)

C007

INA1650-Q1, INA1651-Q1

www.ti.com

SBOS772B – AUGUST 2017 – REVISED APRIL 2019

Product Folder Links: INA1650-Q1 INA1651-Q1

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Typical Characteristics (continued)

at TA = 25°C, VS = ±12 V, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)

100-mV input step

Figure 19. Overshoot vs Capacitive Load

Figure 20. Channel Separation vs Frequency

10-mV input step

Figure 21. Small-Signal Step Response

10-V input step

Figure 22. Large-Signal Step Response

10-V input step, 0.01% settling = ±1 mV

Figure 23. Rising-Edge Settling Time

10-V input step, 0.01% settling = ±1 mV

Figure 24. Falling-Edge Settling Time

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