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54HC109 Datasheet(PDF) 4 Page - Silicon Supplies |
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54HC109 Datasheet(HTML) 4 Page - Silicon Supplies |
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4 / 6 page ![]() High Speed CMOS Logic – 54HC109 DC Electrical Characteristics (Voltages Referenced to GND) Rev 1.0 16/4/18 LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS FULL RANGE 4 25°C 85°C 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 VIN = VIH or VIL │IOUT│≤ 20µA 6.0V 0.1 0.1 0.1 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.40 Maximum Low-Level Output Voltage VOL V VIN = VIL 6.0V │IOUT│≤ 5.2mA 0.26 0.33 0.40 Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent VIN = VCC or GND Supply Current ICC 6.0V IOUT = 0µA 4 40 80 µA AC Electrical Characteristics5 LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS FULL RANGE 4 25°C 85°C 2.0V 6.0 4.8 4.0 4.5V 30 24 20 Maximum Clock Frequency CL = 50pF, (50% Duty Cycle) (Figure 1,4) fmax MHz tr = tf = 6ns 6.0V 35 28 24 2.0V 175 220 265 4.5V 35 44 53 Maximum Propagation Delay, CL = 50pF, Clock to Q or Q (Figure 1,4) tPLH, tPHL ns tr = tf = 6ns 6.0V 30 37 45 2.0V 230 290 345 4.5V 46 58 69 Maximum Propagation Delay, Set or Reset to Q or Q (Figure 2,4) tPLH, tPHL 6.0V CL = 50pF, tr = tf = 6ns 39 49 59 ns 2.0V 75 95 110 4.5V 15 19 22 Maximum Output Rise and Fall Time (Figure 1,4) tTLH, tTHL 6.0V CL = 50pF, tr = tf = 6ns 13 16 ns 19 Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation TJ = 25°C, pF Capacitance (Per Flip-Flop) 6 CPD - VCC = 5.0V 40 5. Not production tested in die form, characterized by chip design and tested in packagE. 6. Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. Page 4 of 6 www.siliconsupplies.com |
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