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High Speed CMOS Logic – 54HC109

Rev 1.0

16/4/18

 

 

Pad Layout and Functions

 

 

  

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1450µm (57.09 mils)

COORDINATES (mm)

0,0

PAD

FUNCTION

X

Y

1

RESET 1

0.130

0.375

2

J1

0.140

0.135

3

K1

0.395

0.145

4

CLOCK 1

0.625

0.145

5

SET 1

0.850

0.145

6

Q1

1.035

0.165

7

Q1

1.220

0.420

8

GND

1.230

0.700

9

Q2

1.230

0.890

10

Q2

1.220

0.935

11

SET 2

1.045

0.935

12

CLOCK 2

0.815

0.935

13

K2

0.585

0.935

14

J2

0.360

0.935

15

RESET 2

0.130

0.900

16

0.120

0.605

Truth Table

Logic Diagram

1

2 

3 

4 

6

7

9

10

11

12 

13 

14 

15 

5 

DIE ID 

16 

8

Pad 8 = GND

* Both outputs will remain high as long as Set and Reset

are low, but the output states are unpredictable if Set and

Reset go high simultaneously.

 

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