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54HC109 Datasheet(PDF) 5 Page - Silicon Supplies |
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54HC109 Datasheet(HTML) 5 Page - Silicon Supplies |
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5 / 6 page ![]() Page 5 of 6 www.siliconsupplies.com High Speed CMOS Logic – 54HC109 Rev 1.0 16/4/18 Timing Requirements5 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS 2.0V 100 125 150 4.5V 20 25 30 Minimum Setup Time, J or K to Clock (Figure 3) tsu 6.0V Input tr = tf = 6ns 17 21 26 ns 2.0V 5 5 5 4.5V 5 5 5 Minimum Hold Time, Clock to J or K (Figure 3) th 6.0V Input tr = tf = 6ns 5 5 5 ns 2.0V 5 5 5 4.5V 5 5 5 Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) trec 6.0V Input tr = tf = 6ns 5 5 5 ns 2.0V 80 100 120 4.5V 16 20 24 Minimum Pulse Width, Set or Reset (Figure 2) tw 6.0V Input tr = tf = 6ns 14 17 20 ns 2.0V 80 100 120 4.5V 16 20 24 Minimum Pulse Width, Clock (Figure 2) tw 6.0V Input tr = tf = 6ns 14 17 20 ns 2.0V 1000 1000 1000 4.5V 500 500 500 Maximum Input Rise and Fall Times (Figure 1) tr, tf 6.0V Input tr = tf = 6ns 400 400 400 ns Switching Waveforms Figure 2 Figure 1 |
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