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GPL16258VB Datasheet(PDF) 17 Page - Generalplus Technology Inc.

Part # GPL16258VB
Description  Advanced Virtual 3D Game / ELA SoC with u nSP 2.0
PDF  23 Pages
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Manufacturer  GENERALPLUS [Generalplus Technology Inc.]
Direct Link  http://www.generalplus.com
Logo GENERALPLUS - Generalplus Technology Inc.

GPL16258VB Datasheet(HTML) 17 Page - Generalplus Technology Inc.

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GPL16258VB
© Generalplus Technology Inc.
Proprietary & Confidential
17
Nov. 24, 2016
Version: 1.0
7. RECOMMENDED BOARD LAYOUT
7.1. Power and Ground
All digital power and ground should be connected.
The decoupling
capacitor of 0.1
F and 10F should be connected to each power
pin of the IC as the following diagram.
The power of analog parts
should be connect from the power source with high quality.
GPL16258VB
DVCC18 (5 pins)
DVSS
0.1
F
10
F
DVCC33 (11 pins)
DVSS
0.1
F
10
F
PLL_V33
PLLGND
0.1
F
10
F
PLLGND
0.1
F
10
F
PLL_V18
7.2. Crystal and PLL
When the 32768Hz crystal is disabled, usually for TV and USB
application, please refer to the following diagram for crystal circuit.
X6MI
X6MO
6MHz
X32KI
X32KO
CL2*
32768 Hz
CL2*
CL1*
CL1*
IOB[2]
Optional
Note*: Please refer to the crystal
’s application circuit.
When the 6MHz crystal is disabled, please refer to the following
diagram to connect the crystal circuit.
X6MI
7.5K
47n
3.3n
X32KI
X32KO
32768 Hz
CL2*
CL2*
IOB[2]
7.3. Analog Section
A specific AGND ground plane should be provided, which connects
by a single trace to the GND ground.
No digital signals should
cross the AGND plane.
DAVREF should be connected to a 1
F
capacitor.
VDVREF should be connected to a 0.1
F capacitor.



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