GS2989

Final Data Sheet

Rev.6

GENDOC-052133

July 2015

5 of 20

Semtech

www.semtech.com

7*

DISABLE2

Input

Control signal input.

When set LOW, the second serial data output is disabled (powered-down) and the

SDO2/SDO2 pins are set to high-impedance.

When set HIGH, the SDO2/SDO2 pins will output a serial data signal.

Note: if this pin is left floating, the second serial data output will be disabled.

9,10

SDO2/

SDO2

Output

Serial data differential output of second output buffer.

11,12

SDO1/

SDO1

Output

Serial data differential output of first output buffer.

14

OSP

Output

Output signal presence status signal output.

Signal levels are LVCMOS/LVTTL compatible.

Indicates presence of a valid output signal.

When the OSP pin is LOW, a good input signal has been detected within the output

stage pre-driver.

When this pin is HIGH, the output signal is invalid at the output of the pre-driver.

15

SD/HD

Input

Control signal input.

When set HIGH, the serial data outputs will meet the SMPTE 259M rise/fall time

specification.

When set LOW, the serial outputs will meet the SMPTE 292M and SMPTE 424M rise/fall

time specification.

Note: if this pin is left floating, the serial data outputs will meet the SMPTE 259M

rise/fall time specification.

16

EQ_EN

Input

Control signal input.

When set LOW, trace-equalization is turned ON.

When set HIGH, trace-equalization is turned OFF.

Note 1: if this pin is left floating, trace-equalization is turned OFF.

Note 2: this pin must be pulled HIGH or left floating for operation in SD mode.

—

Center Pad

Power

Connect to most negative power supply plane following the recommendations in

Recommended PCB Footprint on page 17.

*

powered-down. In this state, minimum power consumption occurs.

Table 1-1: Pin Descriptions (Continued)

Pin Number

Name

Type

Description