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GS3471 Datasheet(PDF) 159 Page - Semtech Corporation

Part # GS3471
Description  3G, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
PDF  179 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS3471 Datasheet(HTML) 159 Page - Semtech Corporation

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GS3471
Final Data Sheet Rev.4
PDS-060498
September 2017
159 of 179
Semtech
www.semtech.com
B09
INT_ENABLE
RSVD
15:15
—
—
Reserved.
EN_NOT_LOCKED
14:14
RW
0
Asserts interrupt when LOCKED signal is not
asserted.
EN_NO_VIDEO
13:13
RW
0
Asserts interrupt when video format is
unknown.
EN_CSUM_ERROR
12:12
RW
0
Asserts interrupt when checksum error is
detected.
EN_ACS_DET3_4B
11:11
RW
0
Asserts interrupt when ACS_DET3_4B flag is
set.
EN_ACS_DET1_2B
10:10
RW
0
Asserts interrupt when ACS_DET1_2B flag is
set.
EN_ACS_DET3_4A
9:9
RW
0
Asserts interrupt when ACS_DET3_4A flag is
set.
EN_ACS_DET1_2A
8:8
RW
0
Asserts interrupt when ACS_DET1_2A flag is
set.
EN_CTRB_DET
7:7
RW
0
Asserts interrupt when CTRB_DET flag is set.
EN_CTRA_DET
6:6
RW
0
Asserts interrupt when CTRA_DET flag is set.
EN_DBNB_ERR
5:5
RW
0
Asserts interrupt when DBNB_ERR flag is set.
EN_DBNA_ERR
4:4
RW
0
Asserts interrupt when DBNA_ERR flag is
set.
EN_ADPG4_DET
3:3
RW
0
Asserts interrupt when ADPG4_DET flag is
set.
EN_ADPG3_DET
2:2
RW
0
Asserts interrupt when ADPG3_DET flag is
set.
EN_ADPG2_DET
1:1
RW
0
Asserts interrupt when ADPG2_DET flag is
set.
EN_ADPG1_DET
0:0
RW
0
Asserts interrupt when ADPG1_DET flag is
set.
Table 5-11: SD Audio Core CSR Descriptions (Continued)
Addressh
Register Name
Parameter Name
Bit
R/W
Reset
Value
Description



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