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AW9920STR Datasheet(PDF) 12 Page - Shanghai awinic technology co.,ltd |
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AW9920STR Datasheet(HTML) 12 Page - Shanghai awinic technology co.,ltd |
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12 / 16 page ![]() AW9920 September 2017 V1.0 www.awinic.com.cn 12 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD PCB LAYOUT CONSIDERATION Follow the advice below when designing PCB layout to optimize the performance of AW9920: Place Cin, Cout closed to Vin, Vout respectively and ground well to decrease noise. To reduce parametric resistance and inductance, keep the Vin-Inductor-Schottky-Output in a straight line and route as short and wide as possible. To reduce parametric influence, minimize the SW-VOUT-GND high-frequency and high- voltage loop as shown below. SW 1 2 GND 3 EN VIN 5 4 ILED Vin L1 D1 Cout Cin Vout GND GND EN Minimize the SW-GND loop area Place close to chip Figure 6 PCB Layout Reference Design |
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