ADM2486 datasheet(16/20 Pages) AD

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ADM2486

Rev. C | Page 16 of 20

APPLICATIONS INFORMATION

POWER_VALID INPUT

To avoid chatter on the A and B outputs caused by slow power-

up and power-down transients on VDD1 (>100 µs/V), the device

features a power_valid (PV) digital input. This pin should be

driven low until VDD1 exceeds 2.0 V. When VDD1 is greater than

2.0 V, this pin should be driven high. Conversely, upon power-

down, PV should be driven low before VDD1 reaches 2.0 V.

If the PV pin is driven with an open-drain output, the

recommended value for the pull-up resistor is a 10 kΩ resistor,

bypassed with a 100 pF capacitor to GND1 (see Figure 30).

The power_valid input can be driven, for example, by the

output of a system reset circuit such as the ADM809Z, which

has a threshold voltage of 2.32 V.

ADM809Z

ADM2486

VDD1

GND1

VDD1

RESET

VDD1

tPOR

2.32V

2.0V

2.32V

2.0V

Figure 29. Driving PV with ADM809Z

ADM809Z

ADM2486

VDD1

GND1

VDD1

RESET

VDD1

tPOR

2.32V

2.0V

2.32V

2.0V

100pF

10k

Ω

Figure 30. Driving PV with an Open-Drain Output

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