AM5728 datasheet(196/415 Pages) TI1

196 / 415 page

vddshv1, vddshv2, vddshv3,

vddshv4, vddshv6, vddshv7,

vddshv9, vddshv10, vddshv11,

vddshv8

(Note 2)

vdds18v

Vdelta

(Note1)

SPRS85v_ELCH_06

196

AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: AM5729 AM5728 AM5726

Specifications

(7) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.

vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If

vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must ensure that the vddshv[1-7,9-11] rail is never

higher than 2.0 V above the vdds18v rail.

(8) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp

down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other

vddshv[1-7,9-11] rails, then it is allowed to ramp down at either of the last two points in the timing diagram.

(9) The 1.8V vdda_* supplies can either ramp down at the earlier time period shown or can be delayed to ramp down after the core supplies

coincident with the vdds18v supply as long as porz is asserted (low) during the power down sequence.

(10) The power down sequence shown is the most general case and is always valid. An accelerated power down sequence is also available

but is only valid when porz is asserted (low). This accelerated power down sequence has been implemented in the companion PMIC

that is recommended for use with this SOC. The accelerated sequence has porz go low first, then all 3.3V supplies simultaneously

second, core supplies, DDR supplies and DDR references simultaneously third and all 1.8V supplies simultaneously last.

(11) Ramped Down is defined as reaching a voltage level of no more than 0.6V.

(12) ddr1_vref0 / ddr2_vref0 may fall coincident with vdds_ddr1 / vdds_ddr2, respectively or at a prior time but after porz is asserted low.

Figure 5-4 describes vddshv[1-7,9-11] Supplies Falling Before vdds18v Supplies Delta.

Figure 5-4. vddshv* Supplies Falling After vdds18v Supplies Delta

(1) Vdelta MAX = 2V

(2) If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.

AM5728 Datasheet(PDF) 196 Page - Texas Instruments