AM5728 datasheet(194/415 Pages) TI1

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194

AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: AM5729 AM5728 AM5726

Specifications

- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails.

If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.

When using RTC mode timing:

- vdda_rtc rises coincident with, or before, the 1.8V interface supplies (such as vdds18v).

- vdd_rtc rises coincident with vdd, or it may rise earlier. If rising earlier, it must rise after the 1.8V interface supplies.

- vddshv5 rises coincident with the other vddshvn rails (of the same voltage) or it can rise about the same time as the 1.8V PHY

supplies (such as vdd_usb1).

(4) vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.

(5) vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.

(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.

(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn

rails but vddshv8 must ramp after vdd.

(8) vdds and vdda rails must not be combined together, with the one exception of vdda_rtc when RTC-mode is not supported.

(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.

(10) The FUNC_32K_CLK source must be stable and at a valid frequency 1ms prior to deasserting rtc_porz high.

(11) porz must remain asserted low until all of the following conditions are met:

–

All device supply rails reach stable operational levels.

–

xi_osc0 is stable and at a valid frequency.

–

Minimum of 12P after both of the above conditions are met, where P = 1 / (SYS_CLK1/610), units in ns.

resetn must be high prior to, or rise simultaneous with, porz but not before its power supply, vddshv3, rising.

(12) Setup time: sysboot[15:0] pins must be valid 2P(15) before porz is de-asserted high.

(13) Hold time: sysboot[15:0] pins must be valid 15P(15) after porz is de-asserted high.

(14) rstoutn will be asserted low when porz is low, and de-asserted following an internal 2ms delay. rstoutn is only valid after vddshv3

reaches an operational level. If used as a peripheral component reset, it should be AND gated with porz to avoid possible reset glitches

during power up.

(15) P = 1/(SYS_CLK1/610) frequency in ns.

(16) ddr1_vref0 / ddr2_vref0 may rise coincident with vdds_ddr1 / vdds_ddr2, respectively or at a later time. However, it must be valid

before porz rising.

AM5728 Datasheet(PDF) 194 Page - Texas Instruments