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AM5728 Datasheet(PDF) 195 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 195 Page - Texas Instruments

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vdda_abe_per, vdda_ddr, vdda_debug,
vdda_dsp_eve, vdda_gmac_core,
vdda_gpu, vdda_iva, vdda_video,
vdda_mpu, vdda_osc
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_pcie1,
vdda_sata, vdda_usb3
vdds_ddr2, vdds_ddr1,ddr1_vref0 ,
ddr2_vref0
(12)
(12)
vdd, vdd_rtc
(4)
vdd_mpu
vdd_gpu
vdd_dspeve
vdd_iva
vddshv8
vdda33v_usb1, vdda33v_usb2
porz
xi_osc0
SPRS85v_ELCH_05
Note 5
Note 6
Note 8
Note 7
Note 9
195
AM5729, AM5728, AM5726
www.ti.com
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
Submit Documentation Feedback
Product Folder Links: AM5729 AM5728 AM5726
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Figure 5-3. Power-Down Sequencing(10)(11)
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(4) If RTC-mode is not used then the following combinations are approved:
- vdda_rtc can be combined with vdds18v
- vdd_rtc can be combined with vdd
- vddshv5 can be combined with other 1.8V or 3.3V vddshv* rails
If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
When using RTC mode timing:
- vdda_rtc falls coincident with, or later than, the 1.8V interface supplies (such as vdds18v).
- vdd_rtc falls coincident with vdd, or it may fall later. If falling later, it must fall before, or coincident with, the 1.8V interface supplies.
- vddshv5 falls coincident with the other vddshvn rails (of the same voltage) or it can fall about the same time as the 1.8V PHY supplies
(such as vdd_usb1).
(5) vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
(6) vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.



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