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AM5728 Datasheet(PDF) 278 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 278 Page - Texas Instruments |
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278 / 415 page  spim_cs(OUT) spi _sclk m (OUT) spi _sclk m (OUT) spi _ m d(IN) spim_cs(OUT) spi _sclk m (OUT) spi _sclk m (OUT) spi _ m d(IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 PHA=1 EPOL=1 POL=0 POL=1 POL=0 POL=1 SM8 SM9 SM3 SM1 SM2 SM1 SM8 SM9 SM3 SM1 SM2 SM1 SM2 SM3 SM2 SM3 SM4 SM5 SM4 SM5 SM4 SM4 SM5 SM5 SPRS906_TIMING_McSPI_02 278 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Figure 7-34. McSPI - Master Mode Receive Table 7-44, Figure 7-35 and Figure 7-36 present Timing Requirements for McSPI - Slave Mode. Table 7-44. Timing Requirements for SPI - Slave Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SS1 tc(SPICLK) Cycle time, spi_sclk (1) (2) (3) 62.5 ns SS2 tw(SPICLKL) Typical Pulse duration, spi_sclk low (1) 0.45*P (4) ns SS3 tw(SPICLKH) Typical Pulse duration, spi_sclk high (1) 0.45*P (4) ns SS4 tsu(SIMO-SPICLK) Setup time, spi_d[x] valid before spi_sclk active edge (1) 5 ns SS5 th(SPICLK-SIMO) Hold time, spi_d[x] valid after spi_sclk active edge (1) 5 ns SS6 td(SPICLK-SOMI) Delay time, spi_sclk active edge to mcspi_somi transition (1) SPI1/2/3 2 26.1 ns SPI4 2 18 ns SS7 td(CS-SOMI) Delay time, spi_cs[x] active edge to mcspi_somi transition (1) 20.95 ns SS8 tsu(CS-SPICLK) Setup time, spi_cs[x] valid before spi_sclk first edge (1) 5 ns SS9 th(SPICLK-CS) Hold time, spi_cs[x] valid after spi_sclk last edge (1) 5 ns |
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