AM5728 datasheet(282/415 Pages) TI1

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AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Timing Requirements and Switching Characteristics

Table 7-46. Switching Characteristics for QSPI

PARAMETER

DESCRIPTION

Mode

MIN

MAX

UNIT

tc(SCLK)

Cycle time, sclk

Default

Timing

Mode,

Clock

Mode 0

13.02

Default

Timing

Mode,

Clock

Mode 3

20.8

tw(SCLKL)

Pulse duration, sclk low

Y*P-1 (1)

tw(SCLKH)

Pulse duration, sclk high

Y*P-1 (1)

td(CS-SCLK)

Delay time, sclk falling edge to cs active edge, CS3:0

Default

Timing

Mode

-M*P-2.0

(2) (3)

-M*P+2.0

(2) (3)

td(SCLK-CS)

Delay time, sclk falling edge to cs inactive edge, CS3:0

Default

Timing

Mode

N*P-2.0

(2) (3)

N*P+2.0

(2) (3)

td(SCLK-D1)

Delay time, sclk falling edge to d[0] transition

Default

Timing

Mode

-2

tena(CS-D1LZ)

Enable time, cs active edge to d[0] driven (lo-z)

-P-3.5

-P+2.5

tdis(CS-D1Z)

Disable time, cs active edge to d[0] tri-stated (hi-z)

-P-2.5

-P+2.0

td(SCLK-D0)

Delay time, sclk first falling edge to first d[0] transition

PHA=0

Only,

Default

Timing

Mode

-2.45 - P

1 .45 - P

(1) The Y parameter is defined as follows:

If DCLK_DIV is 0 or ODD then, Y equals 0.5.

If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1).

For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on

CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division

factor DCLK_DIV can be found in the device TRM.

(2) P = SCLK period.

(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0.

M=QSPI_SPI_DC_REG.DDx when Clock Mode 3.

N = 2 when Clock Mode 0.

N = 3 when Clock Mode 3.

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