AM5728 datasheet(284/415 Pages) TI1

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sclk

d[0]

d[3:1]

Bit n-1

Bit n-2

Bit 1

Bit 0

PHA=1

POL=1

Command

Write Data

SPRS91v_QSPI_03

284

AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: AM5729 AM5728 AM5726

Timing Requirements and Switching Characteristics

Table 7-47. Timing Requirements for QSPI

PARAMETER

DESCRIPTION

Mode

MIN

MAX

UNIT

Q12

tsu(D-RTCLK)

Setup time, d[3:0] valid before falling rtclk edge

Default

Timing

Mode,

Clock

Mode 0

5.1

tsu(D-SCLK)

Setup time, d[3:0] valid before falling sclk edge

Default

Timing

Mode,

Clock

Mode 3

12.3

Q13

th(RTCLK-D)

Hold time, d[3:0] valid after falling rtclk edge

Default

Timing

Mode,

Clock

Mode 0

-0.1

th(SCLK-D)

Hold time, d[3:0] valid after falling sclk edge

Default

Timing

Mode,

Clock

Mode 3

Q14

tsu(D-SCLK)

Setup time, final d[3:0] bit valid before final falling sclk edge

Default

Timing

Mode,

Clock

Mode 3

12.3-P

(1)

Q15

th(SCLK-D)

Hold time, final d[3:0] bit valid after final falling sclk edge

Default

Timing

Mode,

Clock

Mode 3

0+P (1)

(1) P = SCLK period.

(2) Clock Modes 1 and 2 are not supported.

(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although

nonstandard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that

launch data on the falling edge in Clock Modes 0 and 3.

Figure 7-39. QSPI Write (Clock Mode 3)

AM5728 Datasheet(PDF) 284 Page - Texas Instruments

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