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AM5728 Datasheet(PDF) 289 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 289 Page - Texas Instruments

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8
7
4
4
3
2
2
1
A0
A1
B0
B1
A30 A31
B30 B31 C0 C1
C2 C3
C31
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data In/Receive)
6
5
ACLKR/X (CLKRP = CLKXP = 0)(A)
ACLKR/X (CLKRP = CLKXP = 1)(B)
289
AM5729, AM5728, AM5726
www.ti.com
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
Submit Documentation Feedback
Product Folder Links: AM5729 AM5728 AM5726
Timing Requirements and Switching Characteristics
Copyright © 2015–2019, Texas Instruments Incorporated
(3) R = ACLKR/X period in ns.
A.
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B.
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 7-41. McASP Input Timing
CAUTION
The IO Timings provided in this section are only valid for some McASP usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
Table 7-52, Table 7-53, Table 7-54 and Figure 7-42 present Switching Characteristics Over
Recommended Operating Conditions for McASP1 to McASP8.
Table 7-52. Switching Characteristics Over Recommended Operating Conditions for McASP1 (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
9
tc(AHCLKRX)
Cycle time, AHCLKR/X
20
ns



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