AM5728 datasheet(292/415 Pages) TI1

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B0 B1

A30 A31

B30 B31 C0

C1 C2

C31

AHCLKR/X (Falling Edge Polarity)

AHCLKR/X (Rising Edge Polarity)

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

AXR[n] (Data Out/Transmit)

ACLKR/X (CLKRP = CLKXP = 0)(B)

ACLKR/X (CLKRP = CLKXP = 1)(A)

292

AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Timing Requirements and Switching Characteristics

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

Figure 7-42. McASP Output Timing

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and

DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented in Table 4-3 and described in Device TRM, Chapter

18 - Control Module.

Table 7-55 through Table 7-62 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see

Figure 7-43 through Figure 7-50).

AM5728 Datasheet(PDF) 292 Page - Texas Instruments