AM5728 datasheet(305/415 Pages) TI1

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AM5729, AM5728, AM5726

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SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: AM5729 AM5728 AM5726

Timing Requirements and Switching Characteristics

7.18 Universal Serial Bus (USB)

SuperSpeed USB DRD Subsystem has two instances in the device providing the following functions:

•

USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)

PHY and HS/FS (USB2.0) PHY.

•

USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY.

NOTE

For more information, see the SuperSpeed USB DRD section of the Device TRM.

7.18.1 USB1 DRD PHY

The USB1 DRD interface supports the following applications:

•

USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant

with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum

data rate of 480 Mbps.

•

USB3.0 Super-Speed PHY port (1.8 V): this asynchronous differential super-speed interface is

compliant with the USB3.0 RX/TX PHY standard (USB3.0 standard v1.0) for a maximum data bit rate

of 5Gbps.

7.18.2 USB2 PHY

The USB2 interface supports the following applications:

•

USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant

with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum

data rate of 480 Mbps.

7.19 Serial Advanced Technology Attachment (SATA)

The SATA RX/TX PHY interface is compliant with the SATA standard v2.6 for a maximum data rate:

•

Gen2i, Gen2m, Gen2x: 3Gbps.

•

Gen1i, Gen1m, Gen1x: 1.5Gbps.

NOTE

For more information, see the SATA Controller section of the Device TRM.

7.20 Peripheral Component Interconnect Express (PCIe)

The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus

interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe

subsystem controller has support for PCIe Gen-II mode (5 Gbps per lane) and Gen-I mode (2.5 Gbps per

lane) (Single Lane and Flexible dual lane configuration).

The device PCIe supports the following features:

•

16-bit operation @250 MHz on PIPE interface (per 16-bit lane)

•

Supports 2 ports x 1 lane or 1 port x 2 lanes configuration

•

Single virtual channel (VC0), single traffic class (TC0)

•

Single function in end-point mode

•

Automatic width and speed negotiation

•

Max payload: 128 byte outbound, 256 byte inbound

•

Automatic credit management

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