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AM5728 Datasheet(PDF) 307 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 307 Page - Texas Instruments

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AM5729, AM5728, AM5726
www.ti.com
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
Submit Documentation Feedback
Product Folder Links: AM5729 AM5728 AM5726
Timing Requirements and Switching Characteristics
Copyright © 2015–2019, Texas Instruments Incorporated
Table 7-66. Timing Requirements for DCANx Receive (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
-
td(DCANRX)
Delay time, DCANx_RX pin to receive shift register
15
ns
Table 7-67. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
-
f(baud)
Maximum programmable baud rate
1
Mbps
-
td(DCANTX)
Delay time, Transmit shift register to DCANx_TX pin(1)
15
ns
(1) These values do not include rise/fall times of the output buffer.
7.22 Ethernet Interface (GMAC_SW)
The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication
and can be configured as an ethernet switch. It provides the Gigabit Media Independent Interface (G/MII)
in MII mode, Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent
Interface (RMII), and the Management Data Input/Output (MDIO) for physical layer device (PHY)
management.
NOTE
For more information, see the Gigabit Ethernet Switch (GMAC_SW) section of the Device
TRM.
NOTE
The Gigabit, Reduced and Media Independent Interface n (n = 0 to 1) are also referred to as
MIIn, RMIIn and RGMIIn.
CAUTION
The IO timings provided in this section are only valid if signals within a single
IOSET are used. The IOSETs are defined in the Table 7-72, Table 7-75,
Table 7-80 and Table 7-87.
CAUTION
The IO Timings provided in this section are only valid for some GMAC usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
Table 7-68 and Figure 7-51 present timing requirements for MIIn in receive operation.
7.22.1 GMAC MII Timings
Table 7-68. Timing Requirements for miin_rxclk - MII Operation
NO.
PARAMETER
DESCRIPTION
SPEED
MIN
MAX
UNIT
1
tc(RX_CLK)
Cycle time, miin_rxclk
10 Mbps
400
ns
100 Mbps
40
ns
2
tw(RX_CLKH)
Pulse duration, miin_rxclk high
10 Mbps
140
260
ns
100 Mbps
14
26
ns



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