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AM5728 Datasheet(PDF) 306 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 306 Page - Texas Instruments

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306
AM5729, AM5728, AM5726
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM5729 AM5728 AM5726
Timing Requirements and Switching Characteristics
Copyright © 2015–2019, Texas Instruments Incorporated
•
ECRC generation and checking
•
Configurable BAR filtering
•
Legacy interrupt reception (RC) and generation (EP)
•
MSI generation and reception
•
PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
•
All PCI Device Power Management D-states with the exception of D3cold / L2 state
The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and
the PCI Local Bus Specification, revision 3.0.
NOTE
For more information, see the PCIe Controller section of the Device TRM.
7.21 Controller Area Network Interface (DCAN)
The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
•
Supports CAN protocol version 2.0 part A, B
•
Bit rates up to 1 MBit/s
•
64 message objects
•
Individual identifier mask for each message object
•
Programmable FIFO mode for message objects
•
Programmable loop-back modes for self-test operation
•
Suspend mode for debug support
•
Software module reset
•
Automatic bus on after Bus-Off state by a programmable 32-bit timer
•
Direct access to Message RAM during test mode
•
CAN Rx/Tx pins are configurable as general-purpose IO pins
•
Two interrupt lines (plus additional parity-error interrupts line)
•
RAM initialization
•
DMA support
NOTE
For more information, see the DCAN section of the Device TRM.
NOTE
The Controller Area Network Interface x (x = 1 to 2) is also referred to as DCANx.
NOTE
Refer to the CAN Specification for calculations necessary to validate timing compliance. Jitter
tolerance calculations must be performed to validate the implementation.
Table 7-66 and Table 7-67 present timing and switching characteristics for DCANx Interface.
Table 7-66. Timing Requirements for DCANx Receive
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
-
f(baud)
Maximum programmable baud rate
1
Mbps



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