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AM5728 Datasheet(PDF) 331 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 331 Page - Texas Instruments |
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331 / 415 page  mmc _clk 2 mmc _cmd 2 mmc _dat 2 [7:0] HS2005 HS2005 HS2006 HS2006 HS2001 HS2002L HS2002H MMC2_05 331 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated (1) P = output mmc2_clk period in ns Figure 7-78. eMMC in - HS200 SDR - Transmitter Mode 7.23.2.4 High-speed JC64 DDR, 8-bit data Table 7-110 and Table 7-111 present Timing requirements and Switching characteristics for MMC2 - High speed DDR in receiver and transmitter mode (see Figure 7-79 and Figure 7-80). Table 7-110. Timing Requirements for MMC2 - JC64 High Speed DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DDR3 tsu(cmdV-clk) Setup time, mmc2_cmd valid before mmc2_clk transition 1.8 ns DDR4 th(clk-cmdV) Hold time, mmc2_cmd valid after mmc2_clk transition 1.8 ns DDR7 tsu(dV-clk) Setup time, mmc2_dat[7:0] valid before mmc2_clk transition 1.8 ns DDR8 th(clk-dV) Hold time, mmc2_dat[7:0] valid after mmc2_clk transition Pad Loopbac k (1.8V) 1.8 (1) ns Pad Loopbac k (3.3V) 1.8 ns Internal Loopbac k 1.8 (1) ns (1) This Hold time requirement is larger than the Hold time provided by a typical eMMC component. Therefore, the trace length between the Device and eMMC component must be sufficiently long enough to ensure that the Hold time is met at the Device. Table 7-111. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT DDR1 fop(clk) Operating frequency, mmc2_clk 48 MHz DDR2H tw(clkH) Pulse duration, mmc2_clk high 0.5*P- 0.172 (1) ns DDR2L tw(clkL) Pulse duration, mmc2_clk low 0.5*P- 0.172 (1) ns DDR5 td(clk-cmdV) Delay time, mmc2_clk transition to mmc2_cmd transition 2.9 7.14 ns DDR6 td(clk-dV) Delay time, mmc2_clk transition to mmc2_dat[7:0] transition 2.9 7.14 ns |
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