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AM5728 Datasheet(PDF) 329 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 329 Page - Texas Instruments |
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329 / 415 page  SSDR2 SSDR2 SSDR1 SSDR3 SSDR4 mmc2_clk mmc2_cmd mmc2_dat[7:0] vayu_mmc2_02 SSDR2 SSDR2 SSDR1 SSDR6 SSDR5 SSDR8 SSDR7 mmc2_clk mmc2_cmd mmc2_dat[7:0] vayu_mmc2_01 329 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-106. Switching Characteristics for MMC2 - JC64 Standard SDR Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SSDR1 fop(clk) Operating frequency, mmc2_clk 24 MHz SSDR2H tw(clkH) Pulse duration, mmc2_clk high 0.5*P- 0.172 (1) ns SSDR2L tw(clkL) Pulse duration, mmc2_clk low 0.5*P- 0.172 (1) ns SSDR3 td(clkL-cmdV) Delay time, mmc2_clk falling clock edge to mmc2_cmd transition -16.96 16.96 ns SSDR4 td(clkL-dV) Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -16.96 16.96 ns (1) P = output mmc2_clk period in ns Figure 7-74. MMC/SD/SDIO in - Standard JC64 - Receiver Mode Figure 7-75. MMC/SD/SDIO in - Standard JC64 - Transmitter Mode 7.23.2.2 High-speed JC64 SDR, 8-bit data, half cycle Table 7-107 and Table 7-108 present Timing requirements and Switching characteristics for MMC2 - High speed SDR in receiver and transmitter mode (see Figure 7-76 and Figure 7-77). Table 7-107. Timing Requirements for MMC2 - JC64 High Speed SDR Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT JC643 tsu(cmdV-clkH) Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 5.6 ns JC644 th(clkH-cmdV) Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 2.6 ns JC647 tsu(dV-clkH) Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge 5.6 ns JC648 th(clkH-dV) Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge 2.6 ns |
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