 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AM5728 Datasheet(PDF) 332 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
AM5728 Datasheet(HTML) 332 Page - Texas Instruments |
|
|
332 / 415 page  mmc _clk 2 mmc _cmd 2 mmc _dat 2 [7:0] DDR7 DDR8 DDR7 DDR8 DDR7 DDR8 DDR7 vayu_mmc2_07 DDR8 DDR2H DDR1 DDR2L DDR3 DDR4 332 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated (1) P = output mmc2_clk period in ns Table 7-112 and Table 7-113 present Timing requirements and Switching characteristics for MMC2 - High speed DDR in receiver and transmitter mode During Boot (see Figure 7-79 and Figure 7-80). Table 7-112. Timing Requirements for MMC2 - JC64 High Speed DDR Mode During Boot NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DDR3 tsu(cmdV-clk) Setup time, mmc2_cmd valid before mmc2_clk transition Boot (1.8V) 1.8 ns Boot (3.3V) 1.8 ns DDR4 th(clk-cmdV) Hold time, mmc2_cmd valid after mmc2_clk transition Boot (1.8V) 1.8 (1) ns Boot (3.3V) 1.8 (1) ns DDR7 tsu(dV-clk) Setup time, mmc2_dat[7:0] valid before mmc2_clk transition Boot (1.8V) 1.8 ns Boot (3.3V) 1.8 ns DDR8 th(clk-dV) Hold time, mmc2_dat[7:0] valid after mmc2_clk transition Boot (1.8V) 1.8 (1) ns Boot (3.3V) 1.8 (1) ns (1) This Hold time requirement is larger than the Hold time provided by a typical eMMC component. Therefore, the trace length between the Device and eMMC component must be sufficiently long enough to ensure that the Hold time is met at the Device. Table 7-113. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode During Boot NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DDR1 fop(clk) Operating frequency, mmc2_clk 48 MHz DDR2 H tw(clkH) Pulse duration, mmc2_clk high 0.5*P-0.172 (1) ns DDR2 L tw(clkL) Pulse duration, mmc2_clk low 0.5*P-0.172 (1) ns DDR5 td(clk-cmdV) Delay time, mmc2_clk transition to mmc2_cmd transition Boot (1.8V) 2.9 7.14 ns Boot (3.3V) 2.9 7.14 ns DDR6 td(clk-dV) Delay time, mmc2_clk transition to mmc2_dat[7:0] transition Boot (1.8V) 2.9 7.14 ns Boot (3.3V) 2.9 7.14 ns (1) P = output mmc2_clk period in ns Figure 7-79. MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
