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AM5728 Datasheet(PDF) 336 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 336 Page - Texas Instruments |
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336 / 415 page  336 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated 7.23.3 MMC3 and MMC4—SDIO/SD MMC3 and MMC4 interfaces are compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic SDIO devices, it supports the following applications: • MMC3 8-bit data and MMC4 4-bit data, SD Default speed, SDR • MMC3 8-bit data and MMC4 4-bit data, SD High speed, SDR • MMC3 8-bit data and MMC4 4-bit data, UHS-1 SDR12 (SD Standard v3.01), 4-bit data, SDR, half cycle • MMC3 8-bit data and MMC4 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle • MMC3 8-bit data, UHS-I SDR50 NOTE The eMMC/SD/SDIOj (j = 3 to 4) controller is also referred to as MMCj. NOTE For more information, see the MMC/SDIO chapter of the Device TRM. 7.23.3.1 MMC3 and MMC4, SD Default Speed Figure 7-81, Figure 7-82, and Table 7-115 through Table 7-118 present Timing requirements and Switching characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmitter mode. Table 7-115. Timing Requirements for MMC3 - Default Speed Mode (1) NO. PARAMETER DESCRIPTION MIN MAX UNIT DS5 tsu(cmdV-clkH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 5.11 ns DS6 th(clkH-cmdV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 20.46 ns DS7 tsu(dV-clkH) Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 5.11 ns DS8 th(clkH-dV) Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 20.46 ns (1) i in [i:0] = 7 Table 7-116. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode (2) NO. PARAMETER DESCRIPTION MIN MAX UNIT DS0 fop(clk) Operating frequency, mmc3_clk 24 MHz DS1 tw(clkH) Pulse duration, mmc3_clk high 0.5*P- 0.270 (1) ns DS2 tw(clkL) Pulse duration, mmc3_clk low 0.5*P- 0.270 (1) ns DS3 td(clkL-cmdV) Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -14.93 14.93 ns DS4 td(clkL-dV) Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -14.93 14.93 ns (1) P = output mmc3_clk period in ns (2) i in [i:0] = 7 Table 7-117. Timing Requirements for MMC4 - Default Speed Mode (1) NO. PARAMETER DESCRIPTION MIN MAX UNIT DS5 tsu(cmdV-clkH) Setup time, mmc4_cmd valid before mmc4_clk rising clock edge 5.11 ns DS6 th(clkH-cmdV) Hold time, mmc4_cmd valid after mmc4_clk rising clock edge 20.46 ns DS7 tsu(dV-clkH) Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 5.11 ns DS8 th(clkH-dV) Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 20.46 ns |
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