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AM5728 Datasheet(PDF) 339 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 339 Page - Texas Instruments |
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339 / 415 page  mmcj_clk mmcj_cmd mmcj_dat[i:0] HS1 HS2L HS2H HS5 HS6 HS5 HS6 vayu_mmc3_10 339 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Figure 7-84. MMC/SD/SDIOj in - High Speed - Transmitter Mode 7.23.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode Figure 7-85, Figure 7-86, and Table 7-123, through Table 7-126 present Timing requirements and Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR12 in receiver and transmitter mode. Table 7-123. Timing Requirements for MMC3 - SDR12 Mode (1) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR125 tsu(cmdV-clkH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 25.99 ns SDR126 th(clkH-cmdV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 1.6 ns SDR127 tsu(dV-clkH) Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 25.99 ns SDR128 th(clkH-dV) Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 1.6 ns (1) i in [i:0] = 7 Table 7-124. Switching Characteristics for MMC3 - SDR12 Mode (2) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR120 fop(clk) Operating frequency, mmc3_clk 24 MHz SDR121 tw(clkH) Pulse duration, mmc3_clk high 0.5*P- 0.270 (1) ns SDR122 tw(clkL) Pulse duration, mmc3_clk low 0.5*P- 0.270 (1) ns SDR123 td(clkL-cmdV) Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -19.13 16.93 ns SDR124 td(clkL-dV) Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -19.13 16.93 ns (1) P = output mmc3_clk period in ns (2) i in [i:0] = 7 Table 7-125. Timing Requirements for MMC4 - SDR12 Mode (1) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR125 tsu(cmdV-clkH) Setup time, mmc4_cmd valid before mmc4_clk rising clock edge 25.99 ns SDR126 th(clkH-cmdV) Hold time, mmc4_cmd valid after mmc4_clk rising clock edge 1.6 ns SDR127 tsu(dV-clkH) Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 25.99 ns SDR128 th(clkH-dV) Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 1.6 ns (1) j in [i:0] = 3 Table 7-126. Switching Characteristics for MMC4 - SDR12 Mode (2) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR120 fop(clk) Operating frequency, mmc4_clk 24 MHz SDR121 tw(clkH) Pulse duration, mmc4_clk high 0.5*P- 0.270 (1) ns SDR122 tw(clkL) Pulse duration, mmc4_clk low 0.5*P- 0.270 (1) ns SDR125 td(clkL-cmdV) Delay time, mmc4_clk falling clock edge to mmc4_cmd transition -19.13 16.93 ns |
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