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AM5728 Datasheet(PDF) 338 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 338 Page - Texas Instruments |
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338 / 415 page  mmcj_clk mmcj_cmd mmcj_dat[i:0] HS4 HS8 HS3 HS7 HS1 HS2H HS2L vayu_mmc3_09 338 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-119. Timing Requirements for MMC3 - SD/SDIO High Speed Mode (1) (continued) NO. PARAMETER DESCRIPTION MIN MAX UNIT HS8 th(clkH-dV) Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 2.6 ns (1) i in [i:0] = 7 Table 7-120. Switching Characteristics for MMC3 - SD/SDIO High Speed Mode (2) NO. PARAMETER DESCRIPTION MIN MAX UNIT HS1 fop(clk) Operating frequency, mmc3_clk 48 MHz HS2H tw(clkH) Pulse duration, mmc3_clk high 0.5*P- 0.270 (1) ns HS2L tw(clkL) Pulse duration, mmc3_clk low 0.5*P- 0.270 (1) ns HS5 td(clkL-cmdV) Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -7.6 3.6 ns HS6 td(clkL-dV) Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -7.6 3.6 ns (1) P = output mmc3_clk period in ns (2) i in [i:0] = 7 Table 7-121. Timing Requirements for MMC4 - High Speed Mode (1) NO. PARAMETER DESCRIPTION MIN MAX UNIT HS3 tsu(cmdV-clkH) Setup time, mmc4_cmd valid before mmc4_clk rising clock edge 5.3 ns HS4 th(clkH-cmdV) Hold time, mmc4_cmd valid after mmc4_clk rising clock edge 1.6 ns HS7 tsu(dV-clkH) Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 5.3 ns HS8 th(clkH-dV) Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 1.6 ns (1) i in [i:0] = 3 Table 7-122. Switching Characteristics for MMC4 - High Speed Mode (2) NO. PARAMETER DESCRIPTION MIN MAX UNIT HS1 fop(clk) Operating frequency, mmc4_clk 48 MHz HS2H tw(clkH) Pulse duration, mmc4_clk high 0.5*P- 0.270 (1) ns HS2L tw(clkL) Pulse duration, mmc4_clk low 0.5*P- 0.270 (1) ns HS5 td(clkL-cmdV) Delay time, mmc4_clk falling clock edge to mmc4_cmd transition -8.8 6.6 ns HS6 td(clkL-dV) Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -8.8 6.6 ns (1) P = output mmc4_clk period in ns (2) i in [i:0] = 3 Figure 7-83. MMC/SD/SDIOj in - High Speed - Receiver Mode |
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