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AM5728 Datasheet(PDF) 342 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 342 Page - Texas Instruments |
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342 / 415 page  mmcj_clk mmcj_cmd mmcj_dat[7:0] SDR501 SDR502L SDR502H SDR505 SDR506 SDR505 SDR506 vayu_mmc3_06 mmcj_clk mmcj_cmd mmcj_dat[7:0] SDR504 SDR508 SDR503 SDR507 SDR501 SDR502H SDR502L vayu_mmc3_05 342 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated 7.23.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle Figure 7-89, Figure 7-90, Table 7-131, and Table 7-132 present Timing requirements and Switching characteristics for MMC3 - SDIO High speed SDR50 in receiver and transmitter mode. Table 7-131. Timing Requirements for MMC3 - SDR50 Mode (1) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR503 tsu(cmdV-clkH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 1.48 ns SDR504 th(clkH-cmdV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 1.6 ns SDR507 tsu(dV-clkH) Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 1.48 ns SDR508 th(clkH-dV) Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 1.6 ns (1) i in [i:0] = 7 Table 7-132. Switching Characteristics for MMC3 - SDR50 Mode (2) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR501 fop(clk) Operating frequency, mmc3_clk 64 MHz SDR502 H tw(clkH) Pulse duration, mmc3_clk high 0.5*P- 0.270 (1) ns SDR502L tw(clkL) Pulse duration, mmc3_clk low 0.5*P- 0.270 (1) ns SDR505 td(clkL-cmdV) Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -3.66 1.46 ns SDR506 td(clkL-dV) Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -3.66 1.46 ns (1) P = output mmc3_clk period in ns (2) i in [i:0] = 7 Figure 7-89. MMC/SD/SDIOj in - High Speed SDR50 - Receiver Mode Figure 7-90. MMC/SD/SDIOj in - High Speed SDR50 - Transmitter Mode |
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