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AM5728 Datasheet(PDF) 345 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 345 Page - Texas Instruments |
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345 / 415 page  345 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated The device Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) consists of dual 32-bit Load / Store RISC CPU cores - Programmable Real-Time Units (PRU0 and PRU1), shared, data, and instruction memories, internal peripheral modules, and an interrupt controller (PRU-ICSS_INTC). The programmable nature of the PRUs, along with their access to pins, events and all SoC resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, customer peripheral interfaces, and in off-loading tasks from the other processor cores of the system-on- chip (SoC). The each PRU-ICSS includes the following main features: • 21x Enhanced GPIs (EGPIs) and 21x Enhanced GPOs (EGPOs) with asynchronous capture and serial support per each PRU CPU core • One Ethernet MII_RT module (PRU-ICSS_MII_RT) with two MII ports and configurable connections to PRUs • 1 MDIO Port (PRU-ICSS_MII_MDIO) • One Industrial Ethernet Peripheral (IEP) to manage/generate Industrial Ethernet functions • 1 x 16550-compatible UART with a dedicated 192 MHz clock to support 12Mbps Profibus • 1 Industrial Ethernet timer with 7/9 capture and 8 compare events • 1 Enhanced Capture Module (ECAP) • 1 Interrupt Controller (PRU-ICSS_INTC) • A flexible power management support • Integrated switched central resource with programmable priority • Parity control supported by all memories CAUTION The IO timings provided in this section are only valid if signals within a single IOSET are used. The IOSETs are defined in the Table 7-154 and Table 7-155. NOTE For more information about PRU-ICSS subsystems interfaces, see the device TRM. NOTE To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register. The pad control registers are presented in Table 4-3 and described in Device TRM, Chapter 18 - Control Module. 7.25.1 Programmable Real-Time Unit (PRU-ICSS PRU) 7.25.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing Table 7-135. PRU-ICSS PRU Timing Requirements - Direct Input Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT 1 tw(GPI) Pulse width, GPI 2*P (1) ns 2 tsk(GPI) Skew between GPI[20:0] signals 4.5 ns |
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