 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AM5728 Datasheet(PDF) 341 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
AM5728 Datasheet(HTML) 341 Page - Texas Instruments |
|
|
341 / 415 page  mmcj_clk mmcj_cmd mmcj_dat[i:0] SDR251 SDR252L SDR502H SDR255 SDR256 SDR255 SDR256 vayu_mmc3_14 mmcj_clk mmcj_cmd mmcj_dat[i:0] SDR252H vayu_mmc3_13 SDR251 SDR252L SDR253 SDR254 SDR257 SDR258 341 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-128. Switching Characteristics for MMC3 - SDR25 Mode (2) (continued) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR252L tw(clkL) Pulse duration, mmc3_clk low 0.5*P- 0.270 (1) ns SDR255 td(clkL-cmdV) Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -8.8 6.6 ns SDR256 td(clkL-dV) Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -8.8 6.6 ns (1) P = output mmc3_clk period in ns (2) i in [i:0] = 7 Table 7-129. Timing Requirements for MMC4 - SDR25 Mode (1) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR255 tsu(cmdV-clkH) Setup time, mmc4_cmd valid before mmc4_clk rising clock edge 5.3 ns SDR256 th(clkH-cmdV) Hold time, mmc4_cmd valid after mmc4_clk rising clock edge 1.6 ns SDR257 tsu(dV-clkH) Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 5.3 ns SDR258 th(clkH-dV) Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 1.6 ns (1) i in [i:0] = 3 Table 7-130. Switching Characteristics for MMC4 - SDR25 Mode (2) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR251 fop(clk) Operating frequency, mmc4_clk 48 MHz SDR252 H tw(clkH) Pulse duration, mmc4_clk high 0.5*P- 0.270 (1) ns SDR252L tw(clkL) Pulse duration, mmc4_clk low 0.5*P- 0.270 (1) ns SDR255 td(clkL-cmdV) Delay time, mmc4_clk falling clock edge to mmc4_cmd transition -8.8 6.6 ns SDR256 td(clkL-dV) Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -8.8 6.6 ns (1) P = output mmc4_clk period in ns (2) i in [i:0] = 3 Figure 7-87. MMC/SD/SDIOj in - SDR25 - Receiver Mode Figure 7-88. MMC/SD/SDIOj in - SDR25 - Transmitter Mode |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
