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AM5728 Datasheet(PDF) 344 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 344 Page - Texas Instruments |
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344 / 415 page  344 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Manual IO Timings Modes must be used to ensure some IO timings for MMC4. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-134 Manual Functions Mapping for MMC4 for a definition of the Manual modes. Table 7-134 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-134. Manual Functions Mapping for MMC4 BALL BALL NAME MMC4_MANUAL1 MMC4_DS_MANUAL1 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 3 E25 uart1_ctsn 0 0 0 0 CFG_UART1_CTSN_IN mmc4_clk E25 uart1_ctsn 1147 0 0 0 CFG_UART1_CTSN_OUT mmc4_clk C27 uart1_rtsn 1834 0 307 0 CFG_UART1_RTSN_IN mmc4_cmd C27 uart1_rtsn 0 0 0 0 CFG_UART1_RTSN_OEN mmc4_cmd C27 uart1_rtsn 0 0 0 0 CFG_UART1_RTSN_OUT mmc4_cmd D27 uart2_ctsn 2165 0 785 0 CFG_UART2_CTSN_IN mmc4_dat2 D27 uart2_ctsn 0 0 0 0 CFG_UART2_CTSN_OEN mmc4_dat2 D27 uart2_ctsn 0 0 0 0 CFG_UART2_CTSN_OUT mmc4_dat2 C28 uart2_rtsn 1929 64 613 0 CFG_UART2_RTSN_IN mmc4_dat3 C28 uart2_rtsn 0 0 0 0 CFG_UART2_RTSN_OEN mmc4_dat3 C28 uart2_rtsn 0 0 0 0 CFG_UART2_RTSN_OUT mmc4_dat3 D28 uart2_rxd 1935 128 683 0 CFG_UART2_RXD_IN mmc4_dat0 D28 uart2_rxd 0 0 0 0 CFG_UART2_RXD_OEN mmc4_dat0 D28 uart2_rxd 0 0 0 0 CFG_UART2_RXD_OUT mmc4_dat0 D26 uart2_txd 2172 44 835 0 CFG_UART2_TXD_IN mmc4_dat1 D26 uart2_txd 0 0 0 0 CFG_UART2_TXD_OEN mmc4_dat1 D26 uart2_txd 0 0 0 0 CFG_UART2_TXD_OUT mmc4_dat1 7.24 General-Purpose Interface (GPIO) The general-purpose interface combines eight general-purpose input/output (GPIO) banks. Each GPIO module provides 32 dedicated general-purpose pins with input and output capabilities; thus, the general- purpose interface supports up to 247 pins. These pins can be configured for the following applications: • Data input (capture)/output (drive) • Keyboard interface with a debounce cell • Interrupt generation in active mode upon the detection of external events. Detected events are processed by two parallel independent interrupt-generation submodules to support biprocessor operations • Wake-up request generation in idle mode upon the detection of external events NOTE For more information, see the General-Purpose Interface chapter of the Device TRM. NOTE The general-purpose input/output i (i = 1 to 8) bank is also referred to as GPIOi. 7.25 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) |
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