 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AM5728 Datasheet(PDF) 119 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
AM5728 Datasheet(HTML) 119 Page - Texas Instruments |
|
|
119 / 415 page  119 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Table 4-7. EMIF Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL ddr1_dqm_ecc EMIF1 ECC Data Mask O V26 ddr1_dqs0 Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AH25 ddr1_dqsn0 Data strobe 0 invert IO AG25 ddr1_dqs1 Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AE27 ddr1_dqsn1 Data strobe 1 invert IO AE28 ddr1_dqs2 Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AD27 ddr1_dqsn2 Data strobe 2 invert IO AD28 ddr1_dqs3 Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO Y28 ddr1_dqsn3 Data strobe 3 invert IO Y27 ddr1_dqs_ecc EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when writing and input when reading. IO V27 ddr1_dqsn_ecc EMIF1 ECC Complementary Data strobe IO V28 ddr1_vref0 Reference Power Supply EMIF1 A Y18 EMIF Channel 2 ddr2_csn0 EMIF2 Chip Select 0 O P24 ddr2_cke EMIF2 Clock Enable O U24 ddr2_ck EMIF2 Clock O T28 ddr2_nck EMIF2 Negative Clock O T27 ddr2_odt0 EMIF2 On-Die Termination for Chip Select 0 O R23 ddr2_casn EMIF2 Column Address Strobe O U28 ddr2_rasn EMIF2 Row Address Strobe O T23 ddr2_wen EMIF2 Write Enable O U25 ddr2_rst EMIF2 Reset output (DDR3-SDRAM only) O R24 ddr2_ba0 EMIF2 Bank Address O U23 ddr2_ba1 EMIF2 Bank Address O U27 ddr2_ba2 EMIF2 Bank Address O U26 ddr2_a0 EMIF2 Address Bus O R25 ddr2_a1 EMIF2 Address Bus O R26 ddr2_a2 EMIF2 Address Bus O R28 ddr2_a3 EMIF2 Address Bus O R27 ddr2_a4 EMIF2 Address Bus O P23 ddr2_a5 EMIF2 Address Bus O P22 ddr2_a6 EMIF2 Address Bus O P25 ddr2_a7 EMIF2 Address Bus O N20 ddr2_a8 EMIF2 Address Bus O P27 ddr2_a9 EMIF2 Address Bus O N27 ddr2_a10 EMIF2 Address Bus O N23 ddr2_a11 EMIF2 Address Bus O P26 ddr2_a12 EMIF2 Address Bus O N28 ddr2_a13 EMIF2 Address Bus O T22 ddr2_a14 EMIF2 Address Bus O R22 ddr2_a15 EMIF2 Address Bus O U22 ddr2_d0 EMIF2 Data Bus IO E26 ddr2_d1 EMIF2 Data Bus IO G25 ddr2_d2 EMIF2 Data Bus IO F25 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
