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AM5728 Datasheet(PDF) 120 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 120 Page - Texas Instruments |
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120 / 415 page  120 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Table 4-7. EMIF Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL ddr2_d3 EMIF2 Data Bus IO F24 ddr2_d4 EMIF2 Data Bus IO F26 ddr2_d5 EMIF2 Data Bus IO F27 ddr2_d6 EMIF2 Data Bus IO E27 ddr2_d7 EMIF2 Data Bus IO E28 ddr2_d8 EMIF2 Data Bus IO H23 ddr2_d9 EMIF2 Data Bus IO H25 ddr2_d10 EMIF2 Data Bus IO H24 ddr2_d11 EMIF2 Data Bus IO H26 ddr2_d12 EMIF2 Data Bus IO G26 ddr2_d13 EMIF2 Data Bus IO J25 ddr2_d14 EMIF2 Data Bus IO J26 ddr2_d15 EMIF2 Data Bus IO J24 ddr2_d16 EMIF2 Data Bus IO L22 ddr2_d17 EMIF2 Data Bus IO K20 ddr2_d18 EMIF2 Data Bus IO K21 ddr2_d19 EMIF2 Data Bus IO L23 ddr2_d20 EMIF2 Data Bus IO L24 ddr2_d21 EMIF2 Data Bus IO J23 ddr2_d22 EMIF2 Data Bus IO K22 ddr2_d23 EMIF2 Data Bus IO J20 ddr2_d24 EMIF2 Data Bus IO L27 ddr2_d25 EMIF2 Data Bus IO L26 ddr2_d26 EMIF2 Data Bus IO L25 ddr2_d27 EMIF2 Data Bus IO L28 ddr2_d28 EMIF2 Data Bus IO M23 ddr2_d29 EMIF2 Data Bus IO M24 ddr2_d30 EMIF2 Data Bus IO M25 ddr2_d31 EMIF2 Data Bus IO M26 ddr2_dqm0 EMIF2 Data Mask O F28 ddr2_dqm1 EMIF2 Data Mask O G24 ddr2_dqm2 EMIF2 Data Mask O K23 ddr2_dqm3 EMIF2 Data Mask O M22 ddr2_dqs0 Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading. IO G28 ddr2_dqsn0 Data strobe 0 invert IO G27 ddr2_dqs1 Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading. IO H27 ddr2_dqsn1 Data strobe 1 invert IO H28 ddr2_dqs2 Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading. IO K27 ddr2_dqsn2 Data strobe 2 invert IO K28 ddr2_dqs3 Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF2 memory when writing and input when reading. IO M28 ddr2_dqsn3 Data strobe 3 invert IO M27 ddr2_vref0 Reference Power Supply EMIF2 A N22 |
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