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AM5728 Datasheet(PDF) 121 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 121 Page - Texas Instruments |
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121 / 415 page ![]() 121 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated NOTE The index numbers 1 and 2 which are part of the EMIF1 and EMIF2 signal prefixes (ddr1_* and ddr2_*) listed in Table 4-7, EMIF Signal Descriptions, not to be confused with DDR1 and DDR2 types of SDRAM memories. 4.4.5 General-Purpose Memory Controller (GPMC) NOTE For more information, see the Memory Subsystem / General-Purpose Memory Controller section of the device TRM. Table 4-8. GPMC Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL gpmc_ad0 GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1 in A/D multiplexed mode IO M6 gpmc_ad1 GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2 in A/D multiplexed mode IO M2 gpmc_ad2 GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3 in A/D multiplexed mode IO L5 gpmc_ad3 GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4 in A/D multiplexed mode IO M1 gpmc_ad4 GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5 in A/D multiplexed mode IO L6 gpmc_ad5 GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6 in A/D multiplexed mode IO L4 gpmc_ad6 GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7 in A/D multiplexed mode IO L3 gpmc_ad7 GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8 in A/D multiplexed mode IO L2 gpmc_ad8 GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9 in A/D multiplexed mode IO L1 gpmc_ad9 GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10 in A/D multiplexed mode IO K2 gpmc_ad10 GPMC Data 10 in A/D nonmultiplexed mode and additionally Address 11 in A/D multiplexed mode IO J1 gpmc_ad11 GPMC Data 11 in A/D nonmultiplexed mode and additionally Address 12 in A/D multiplexed mode IO J2 gpmc_ad12 GPMC Data 12 in A/D nonmultiplexed mode and additionally Address 13 in A/D multiplexed mode IO H1 gpmc_ad13 GPMC Data 13 in A/D nonmultiplexed mode and additionally Address 14 in A/D multiplexed mode IO J3 gpmc_ad14 GPMC Data 14 in A/D nonmultiplexed mode and additionally Address 15 in A/D multiplexed mode IO H2 gpmc_ad15 GPMC Data 15 in A/D nonmultiplexed mode and additionally Address 16 in A/D multiplexed mode IO H3 gpmc_a0 GPMC Address 0. Only used to effectively address 8-bit data nonmultiplexed memories O R6/ P4 gpmc_a1 GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D multiplexed mode O T9/ P1 gpmc_a2 GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D multiplexed mode O T6/ N1 gpmc_a3 GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D multiplexed mode O T7/ M4 |
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