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AM5728 Datasheet(PDF) 127 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 127 Page - Texas Instruments

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AM5729, AM5728, AM5726
www.ti.com
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
Submit Documentation Feedback
Product Folder Links: AM5729 AM5728 AM5726
Terminal Configuration and Functions
Copyright © 2015–2019, Texas Instruments Incorporated
Table 4-13. SPI Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Serial Peripheral Interface 4
spi4_sclk(1)
SPI4 Clock
IO
N7/ G1/ AA3/ V7/
AC8
spi4_d1
SPI4 Data. Can be configured as either MISO or MOSI.
IO
R4/ G6/ AB9/ U7/
AD6
spi4_d0
SPI4 Data. Can be configured as either MISO or MOSI.
IO
N9/ F2/ AB3/ V6/
AB8
spi4_cs0
SPI4 Chip Select
IO
P9/ F3/ AA4/ U6/
AB5
spi4_cs1
SPI4 Chip Select
IO
P4/ Y1
spi4_cs2
SPI4 Chip Select
IO
R3/ W9
spi4_cs3
SPI4 Chip Select
IO
T2/ V9
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
4.4.11 Quad Serial Peripheral Interface (QSPI)
NOTE
For more information see the Serial Communication Interface / Quad Serial Peripheral
Interface section of the device TRM.
Table 4-14. QSPI Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
qspi1_sclk
QSPI1 Serial Clock
O
R2
qspi1_rtclk
QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer
to PCB Guidelines for QSPI1.
I
R3
qspi1_d0
QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read
and quad read modes it becomes input data pin during read phase.
IO
U1
qspi1_d1
QSPI1 Data[1]. Input read data in all modes.
I
P3
qspi1_d2
QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during
read phase
I
U2
qspi1_d3
QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during
read phase
I
T2
qspi1_cs0
QSPI1 Chip Select[0]. This pin is Used for QSPI1 boot modes.
O
P2
qspi1_cs1
QSPI1 Chip Select[1]
O
P1
qspi1_cs2
QSPI1 Chip Select[2]
O
T7
qspi1_cs3
QSPI1 Chip Select[3]
O
P6
4.4.12 Multichannel Audio Serial Port (McASP)
NOTE
For more information, see the Serial Communication Interface / Multichannel Audio Serial
Port (McASP) section of the device TRM.
Table 4-15. McASP Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Multichannel Audio Serial Port 1
mcasp1_axr0
McASP1 Transmit/Receive Data
IO
G12



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